User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index

201
Chapter 4: Concepts
Understanding Logic Analyzer Triggering
because timer1 will keep running and condition “Timer1 <500 ns” will
never be met. There might be another rising edge on SIG1 that is
followed within 500ns by the rising edge on SIG2 that occurs later on,
so this situation is unacceptable.
To fix this problem, whenever the timer exceeds 500ns without
triggering, the sequence should loop back to Level 1 to look for another
rising edge on SIG1. The following shows an example of the correct
sequence:
1. If there is a Rising Edge on SIG1, then
Start Timer1
Go to 2
2. If there is a Rising Edge on SIG2 AND Timer1 < 500ns then
Trigger
Else If Timer1 >= 500ns then
Reset Timer1
Go to 1
Occasionally, you may run out of timers. A counter can be used in place
of a timer if the logic analyzer is sampling at regular intervals (that is, if
it's in the timing sampling mode). A timer can be simulated by counting
the number of samples that are acquired. For example, if the logic
analyzer acquires a new sample every 10ns and seven samples are
acquired, this represents 70ns.
Next: “Storage Qualification” on page 201
Storage Qualification
Storage qualification is used to determine if an acquired sample should
be stored (that is, placed in memory) or thrown away. This keeps the
logic analyzer memory from being filled with samples that are not
needed.
Default Storage
The simplest method to set up storage qualification is by setting up the
Default Storage. This is specified separate from the trigger sequence,
such as in a separate tab or another dialog. Default Storage means
“unless a sequence level specifies otherwise, this is what should be
stored”. As an example, you may want to only store samples if ADDR is
in the range 1000 to 2000, so you should set the Default Storage to: