User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index

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Chapter 4: Concepts
Understanding Logic Analyzer Triggering
edge before it begins looking for the next rising edge. Because there is
a sequence of steps to find the trigger, this is known as a trigger
sequence. Each step of the sequence is called a sequence level.
Each sequence level consists of two parts; the conditions and the
actions. The conditions are Boolean expressions such as “If ADDR =
1000” or “If there is a rising edge on SIG1”. The actions are what the
logic analyzer should do if the condition is met. Examples of actions
include triggering the logic analyzer, going to another sequence level,
or starting a timer. This is similar to an If/Then statement in
programming.
Each sequence level in the trigger sequence is assigned a number. The
first sequence level to be executed is always Sequence Level 1, but
because of the Go To actions, the rest of the sequence levels can be
executed in any order.
When a sequence level is executed and none of the Boolean
expressions are true, the logic analyzer acquires the next sample and
executes the same sequence level again. As a simple example, consider
the following trigger sequence:
1. If DATA = 7000 then Trigger
If the following samples were acquired, the logic analyzer would trigger
on sample #6.
Sample # ADDR DATA
1 1000 2000
2 1010 3000
3 1020 4000
4 1030 5000
5 1040 6000
6 1050 7000 <- This is where the logic analyzer triggers
7 1060 2000
In essence, Sequence Level 1 is equivalent to “Keep acquiring more
samples until DATA=7000, then trigger”.
If a Boolean expression in a sequence level is met, another sample is
always acquired before the next sequence level is executed. In other
words, if a sample meets the condition in Sequence Level 1, another
sample will be acquired before executing Sequence Level 2. This
means that it is not possible for a single sample to be used to meet the
conditions of more than one sequence level. Each sequence level can
be thought of as representing events that occur at different points in