User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index

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Chapter 3: Reference
Specifications and Characteristics
General information
- Channel Counts:
1-card module 64 data, 4 clock
2-card module 132 data, 4 clock
3-card module 200 data, 4 clock
4-card module 268 data, 4 clock
5-card module 336 data, 4 clock
Probes (at end of flying lead set)
- Input Resistance: 100 Kohm, +/- 2%
- Parasitic Tip Capacitance: 1.5 pF
- Minimum Voltage Swing: 500 mV peak-to-peak
- Minimum Input Overdrive: 250 mV
- Maximum Voltage: +/- 40 V peak CAT I
- Threshold Range: +/- 6.0 V, adjustable in 10-mV increments
- Power through pod cables: 1/3 amp per pod, not to exceed 1 amp total
State Analysis
- Maximum State Clock Speed: 400 MHz
- Maximum Memory Depth: 4 M
- *Minimum Setup/Hold Time: 4.5/-2.0 ns through -2.0/4.5 ns,
adjustable in 100-ps increments
- Minimum State Clock Width: 1.2 ns
- Minimum Master-to-Master Clock: 5.0 ns at 200 MHz
2.5 ns at 400 MHz
- Minimum Master-to-Slave Clock: 2 ns
- Minimum Slave-to-Slave Clock: 5.0 ns at 200 MHz
2.5 ns at 400 MHz
- State Clocks: 4
- State Clock Qualifiers: 4
- **Time Tag Resolution: 4 ns
- Maximum Time Count Between States: 17 seconds
- **Maximum State Tag Count: 2e32
- Store qualification Default and per sequence level
* Specified for single-edge, single-clock acquisition.
Multi-edge setup/hold window is 3.0 ns.
** When all pods are being used, time or state tags halve the memory
depth.
Timing Analysis
Timing Zoom
- Sample Rates: 2 GHz/1 GHz/500 MHz/250 MHz
- Sample Period Accuracy: +/- 50 ps
- Channel-to-channel Skew: less than 1.0 ns
- Time Interval Accuracy: +/- (sample period + channel-to-
channel skew + 0.01% of time
interval reading)
- Memory Depth: 16 K
Conventional Timing
- Maximum Sample Rate:
Half Channel 800 MHz
Full Channel 400 MHz
- Memory Depth:
Half Channel 8 M samples per channel
Full Channel 4 M samples per channel
- Sample Period Accuracy: +/- (250 ps + 0.01% of sample period)
- Channel-to-Channel Skew: less than 1.5 ns, typical
- Time Interval Accuracy: +/-( sample period + channel-to-
channel skew + 0.01% of time
interval reading )
- Minimum data pulse width: 1.5 ns for data capture,
5.0 ns for trigger sequencing
Transitional Timing
- Maximum timing analysis sample rate: 400 MHz
- Minimum data pulse width: 3.7 ns for data capture,
5.0 ns for trigger sequencing
- Number of channels: For sample rates < 400 MHz: 68 x
(number of modules)