User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index
180
Chapter 3: Reference
Error Messages
Slow or Missing Clock
The message "Slow or Missing Clock" only appears in state
measurements. However, if you have another instrument armed by the
state analyzer, a slow or missing clock on the state analyzer will prevent
the other instrument from triggering also.
Possible Causes
• Target system is not running properly
Check that the system is running properly. The logic analyzer and other
probing fixtures such as pin extenders can place too much capacitive load
on a system.
• Incorrect clock specification
Make sure the device under test clock matches the clock specified under
Sampling.
Also check that the probe's clock channels are attached to the device
under test's clock lines either directly or through an analysis probe.
If you are using an analysis probe, the probe's User's Guide should show
the correct connections and settings.
• Bad probe connection
Check that the probe is securely attached to the clock line and is receiving
a signal. The logic analyzer shows activity indicators under the Sampling
and Format tabs.
• Incorrect signal level
The clock's threshold level is set by the pod threshold. For the logic
analyzer's J clock, check the pod threshold of pod 1 of the master card.
Timer value checked as an event, but no start
action specified
This warning occurs because you have used a timer in your trigger
sequence, but have not started it with either Start from reset or