User's Manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index
164
Chapter 3: Reference
The Symbols Tab
C++ notation. To improve performance for these ELF symbol files, type
information is not associated with variables. Hence, some variables
(typically a few local static variables) may not have the proper size
associated with them. They may show a size of 1 byte and not the
correct size of 4 bytes or even more. All other information function
ranges, line numbers, global variables and filenames will be accurate.
These behaviors may be changed by creating a readers.ini (see
page 101) file.
See Also “To load object file symbols” on page 96
“To create an ASCII symbol file” on page 100
“To create a readers.ini file” on page 101
General-Purpose ASCII (GPA) Symbol File
Format
General-purpose ASCII (GPA) format files are loaded into a logic
analyzer just like other object files.
If your compiler does not produce object files in a supported format, or
if you want to define symbols that are not included in the object file,
you can create an ASCII format symbol file.
Typically, ASCII format symbol files are created using text processing
tools that convert the symbol table information from a compiler or
linker map output file.
Different types of symbols are defined in different records in the GPA
file. Record headers are enclosed in square brackets, for example,
[VARIABLES]. For a summary of GPA file records and associated
symbol definition syntax, refer to the “GPA Record Format Summary”
on page 165 that follows.
Each entry in the symbol file must consist of a symbol name followed
by an address or address range.
While symbol names can be longer, the logic analyzer only uses the first
16 characters.