Specifications

304 Chapter 10
Block Diagrams
CDMA Generator Section
Figure 10-14 Data Buffer Assembly, A2A34
DATA
BUFFER
128Kx8
SRAM
BUFF
DATA
BUFFER
CONTROL
SERIAL
I.O.
MODNOISE
NOISE
SOURCE
CDMA
REVERSE
LINK
MODULATOR
SERIAL
CONTROL
PARALLEL OUTPUTS
CLOCK/SYNC FROM GEN/REF BD
DATA
12
12
12
8
8
8
I NOISE CONTROL
Q NOISE CONTROL
GAUSSIAN TABLE/
BUFF/MODNOISE
CONFIG
128Kx16
FLASH
DAC
1 MHz
DAC
1 MHz
CAL
EEPROM
DAC
DAC
I SIGNAL
GAIN DELTA
Q SIGNAL CONTROL
I SIGNAL CONTROL
FROM
MEMORY/
PARALLEL
OUTPUTS
CLOCK/SYNC FROM GEN/REF BD
EMO
SERIAL BUS
STATUS/
READBACK
s_CLK
s_DATA
u_lds (L)
u_r/w (L)
uaddr 1, 15-19
8
6
udata 0-7
DATA IN
SMB
SMB
SMB
MOTHERBOARD
TO IQ MODULEATOR
I
Q
SMBSMB
DIAG
INTERNAL
DIAG LINES
DIAG_OUT
DIAG
MUX
DIAG TO
MEASUREMENT
BOARD
SERIAL_DATA
SMB
SMB
BASEBAND
OUTPUT
(SIDE PANEL)
FROM
CDMA GEN/REF
I
Q
16X CHIP
SBRC
SIDE
PANEL
TO CDMA GEN/REF