Specifications

Chapter 10 301
Block Diagrams
CDMA Analyzer Section
Figure 10-12 Receive DSP Assembly, A2A36
RECEIVE DSP ASSEMBLY, A2A36
SMB
-10 TO +30 dB
GAIN
8 MHz
12 BIT
ADC
DE-MUX
12 TO 24
SAMPLE
CLOCK
GENERATOR
128K FLASH
EPROM
256K FAST RAM
TMS320C30
DSP
RESET
1
INTO
1
SERIAL PORT 1
SERIAL PORT 2
6
TCLKO/1
6
2
ADDR
DECODE
3
DATA
BUFFER
DATA
LATCHES
(4)
DAC
MUX
TRIG
CKT
EXT TRIGGER
SMB
2
INT0, INT1
Fs
Fs/2
TRIG_OUT NC
EXT
Fs
PRIMARY
BUS DATA
ADDR
32
24
33 MHz
INTMED
12
XF1
EXP BUS
512x8
BI-FIFO
1
DIAG
31
PWR
+
15.
-
5
V
-
+
100 ohm
DET_OUT
FROM
RF IO ASSY
D_RCV_
DSP_TRIG
NC
NC
NC
NC
6
NC
NC
14
NC
SMB
(FROM
CDMA GEN/REF)