User`s guide

Chapter 4 Theory of Operation
Floating Logic
90
Floating Logic
The floating common logic controls operation of the entire instrument. All output
functions and bus command interpretation is performed in the main controller U19.
The front panel and the earth referenced logic operate as slaves to U19. The floating
common logic is comprised of the main controller U19, custom gate array U20, the
program ROM U13, RAM U14, calibration EEPROM U15, and the 12 MHz clock
oscillator. Non-volatile EEPROM U15 stores calibration constants, calibration secure
code, calibration count, and store/recall variables. Power-on reset is provided to the
main controller by the voltage regulator U10.
The main controller U19 is a 16-bit micro controller. It controls such features as
receive and transmit serial port, timer/counter ports, and selectable input 10-bit
successive approximation A-to-D converter ports.
A conventional address/data bus is used to transfer data between the main controller
and external ROM and RAM. When the address latch enable (ALE) signal goes high,
address data is present on the address/data bus. ASIC U20 latches the address data
and decodes the correct chip enable (low true) for external ROM and RAM accesses
and for read/write accesses to the internal registers of U20. The system memory map
is shown below.
Program ROM U13 contains four 64k x 8 data banks of data. Banks are selected by
controlling A16 and A17 ROM address bits directly from the main controller port bits.
Custom gate array U20 performs address latching and memory map decoding
functions as discussed above. In addition, U20 contains a variety of internal read/write
registers. The read (XRD) and write (XWR) signals transfer data out of and into U20
when it is addressed. There are four internal registers in U20: an internal configuration
register, an 8 bit counter register, a serial transmit/receive register, and an internal
status register.
The counter register is used to capture the ADC slope count at the COMP input. The
COMP input functions as both a clocked comparator and the slope counter input for
the ADC. In both cases the counter register captures the lower 8 bits of a 24-bit counter.
The upper 16 bits of the count are captured by the SYNC input to U19.
The serial register is used to send and receive serial data bytes from the main controller
to the DAC system, or to communicate with the front panel controller. The serial
register is multiplexed to these two circuits. The transmission rate is selected to 1.5
0000
H
- 1FF7
H
U14 32k x 8 RAM
1FF8
H
- 1FFF
H
U20 Gate Array
2000
H
- FFFF
H
U13 Program ROM