User`s guide

Chapter 5 Service
Self-Test Procedures
106
Self-Test Procedures
Power-On Self-Test
Each time the power supply is powered on, a set of self-tests are performed. These
tests check that the minimum set of logic and measurement hardware are functioning
properly. The power-on self-test performs checks 601 through 604 and 624 through
632. For serial MY53xx6xxx, the power-on self-test utilizes the complete self-test,
which covers error codes 601 through 632.
Complete Self-Test
Hold any front panel key except the ‘‘Error’’ key for more than 5 seconds while turning
on the power to perform a complete self-test. The power supply beeps when the test
starts. The tests are performed in the order shown below.
601
Front Panel Does not respond The main controller U19 (U101 for serial
MY53xx6xxx) attempts to establish serial communications with the front panel
controller U1 (U602 for serial MY53xx6xxx) on the front panel board. During this
test, the U1 (U602 for serial MY53xx6xxx) turns on all display segments.
Communication must function in both directions for this test to pass. If this error is
detected during power-on self-test, the power supply will beep twice. This error is
only readable from the remote interface.
602
RAM read/write failed This test writes and reads a 55h and AAh checker board
pattern to each address of ram U14 (on-chip RAM for serial MY53xx6xxx). Any
incorrect readback will cause a test failure. This error is only readable from the remote
interface.
603
A/D sync stuck The main controller issues an A/D sync pulse to U19 and U20 to
latch the value in the ADC slope counters. A failure is detected when a sync interrupt
is not recognized and subsequent time-out occurs.
604
A/D slope convergence failed The input amplifier is configured to the measure zero
(MZ) state in the 10 V range. This test checks whether the ADC integrator produces
nominally the same number of positive and negative slope decisions (±10%) during
a 20 ms interval.
605
Cannot calibrate rundown gain This test checks the nominal gain between
integrating ADC and the U19 on-chip ADC. This error is reported if the procedure
cannot run to completion due to a hardware failure.