Specifications

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Chapter 3: Testing Performance
Test Pod 1 in the 1250 Mb/s mode
tab. In the “State Mode Controls” section, select the “1250 Mb/s / 128M
Half Chan” mode. The clock mode will change to “Both Edges”.
11 In the logic analyzer’s Setup and Trigger window, Format tab, unassign all
pod 2 bits. The channel assignment dialog looks different in half-channel
mode because only half of the channels can be assigned now.
12 Assign bits 2, 6, 10, and 14 of Pod 1.
13 Verify that the Pod 1 threshold is set to 1 volt. See page 53.
14 In the “Setup and Trigger...” window, Format tab, verify that the J clock
threshold is still set to Differential.
15 Re-establish the trigger function:
a In the logic analyzer’s Setup and Trigger window, select the Trigger tab,
and the Trigger Functions subtab.
b Select “Find pattern n times” and select the “Replace” button.
c Enter “A” in the “Label 1 = “ field.
Determine and set Eye Finder Position (1250 Mb/s
mode)
In the 1250 Mb/s mode, only double-edge clocking (“Both Edges”) is
available. Therefore, we will use a different method for ensuring that we
are measuring the correct eye.
16 Set the pulse generator frequency to half of the required value. If it was set
to 638 MHz, then temporarily set it to 319 MHz.
17 In the Eye Finder (Sampling Positions) window, expand “Label1 (4
channels)”.
18 Grab the blue bar for “Label1 (4 Channels)” and move it to approximately
-0.94 ns. All blue bars will follow.
19 Run Eye Finder and note the average sampling position chosen by Eye
Finder:______ns. In the following example, the average sampling position
is -0.94 ns. Note that in this step, you place the blue bars in the first
narrow window (not the wide window) that appears to the left of zero in
the Eye Finder display. Then run Eye Finder. The position may be
different based on your test setup. Bring stray channels into alignment if