Specifications

Chapter 3: Testing Performance

Test Pod 1 in the 400 Mb/s mode

1 Disconnect the Pod 2 E5382A Flying Lead Probe Set’s bits 2, 6, 10, and 14

from the SMA/Flying Lead test connectors’ pin strip connectors.

The original E5382A Flying Lead Probe Set should still be connected to

Pod 1. The J clock on Pod 1 will be used for all tests.

2 Connect the Pod 1 E5382A Flying Lead Probe Set’s bits 6 and 14 to the

SMA/Flying Lead test connector’s pin strip connector at the 8133A pulse

generator’s Channel 2 OUTPUT.

3 Connect the Pod 1 E5382A Flying Lead Probe Set’s bits 2 and 10 to the

SMA/Flying Lead test connector’s pin strip connector at the 8133A pulse

generator’s Channel 2 OUTPUT.

4 On the 8133A pulse generator, in the PULSE setup for CHANNEL 2, press

the COMP button to return the outputs to normal.

5 Note that the signal on the oscilloscope has moved. Change the

oscilloscope’s horizontal position to 800 ps (or as required) to center the

measured pulse on the oscilloscope display.

6 Verify the DC offset and adjust it if necessary. See page 46.

7 Set the frequency of the pulse generator. The logic analyzer will be tested

using a double-edge clock. The test frequency is half the test clock rate

because data is acquired on both the rising edge and the falling edge of the

clock. Set the frequency to 200 MHz plus the frequency uncertainty of the

pulse generator, plus a test margin of 1%.

For example, if you are using an 8133A pulse generator, the frequency

accuracy is ±1% of setting. Use a test margin of 1%. Set the frequency to

200 MHz plus 2% (204 MHz).

8 Verify the oscilloscope Deskew and adjust if necessary. See page 47.

9 Adjust the measured pulse width from the pulse generator to 1.5 ns

(minus the test margin) as described on page 48.

10 In the logic analyzer “Setup and Trigger...” window, select the Sampling

tab. In the “State Mode Controls” section, select the “400 Mb/s / 32M State”

mode. The mode will change to 400 Mb/s and the clock setup will change

to “Rising Edge.”

11 In the logic analyzer’s Setup and Trigger window, Format tab, unassign all