Specifications

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Chapter 3: Testing Performance
16760A Minimum Data Eye Width and Minimum Clock Interval Performance Test Procedure
16760A Minimum Data Eye Width and Minimum Clock
Interval Performance Test Procedure
The specifications for the 16760A logic analyzer define a minimum data eye width
and a minimum clock interval at which data can be acquired.
These tests verify that the logic analyzer meets these specifications.
At each of the five acquisition modes, we will test the minimum data eye width at
the minimum clock interval, thereby testing both specifications at once.
The minimum clock interval is specified from active clock edge to active clock
edge. All tests are performed while clocking data into the logic analyzer on both
rising and falling edges of the clock (double edge clock), so the pulse generator
test frequency will be set to half of the acquisition speed.
Eye Finder is used to adjust the sampling position on every channel. Eye Finder
must be used to achieve minimum data eye width.
Acquisition Mode: 200 Mb/s 400 Mb/s 800 Mb/s 1.25 Gb/s 1.5 Gb/s
Minimum clock interval,
active edge to active edge
5 ns 2.5 ns 1.25 ns 800 ps 667 ps
Minimum data pulse width 1.5 ns 1.5 ns 750 ps 750 ps 600 ps