Specifications

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Chapter 8: Theory of Operation
CPU Interface. The CPU interface is a programmable logic device that converts
the bus signals generated by the microprocessor on the mainframe CPU card into
control signals for the logic analyzer module. All functions of the state and timing
module can be controlled from the backplane of the mainframe system including
storage qualification, sequencing, assigning clock edges, RUN and STOP, and
thresholds. Data transfer between the logic analyzer cards and the mainframe
CPU is also accomplished through the CPU interface.
Master/Expander Configuration
Connectors J3 and J8 route clock and signals for operational accuracy calibration
to expander boards in a master/expander multicard module. The master-
configured module has the common connector (J3) cabled to the master
connector (J6) expander board have their common connector cabled to the
expander connectors (J4, J5, J7, and J8) of the master-configured board. Clock
signals generated from either the master acquisition IC (timing mode) or from
the system under test (state mode) are distributed to the expander boards
through the master/expander star connectors. Clock generation is disabled to all
expander boards. Additionally, a pattern found signal is routed from all
configured expander boards to the master board through the star connectors.
When the module is in pattern search mode, the pattern found signal is asserted
by the expander board with the found pattern.