Specifications

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Chapter 8: Theory of Operation
state clock modes and configuration are also done by the comparators. A digital-
to-analog convertor (DAC) provides the module threshold voltage for single-
ended operation. The voltage at the DAC outputs are buffered to prove sufficient
line drive. An analog switch is used to channel either the module threshold
voltage from the DAC or the threshold voltage input from the system under test
to the comparators.
High Speed Gate Array. The high speed gate arrays sample the incoming data
in the high speed state modes. The gate arrays have differential inputs and single-
ended outputs and translate the incoming data from differential to single-ended
signals. The output of the high speed gate arrays is channeled to the input of the
acquisition ICs. A synchronizing signal ensures the gate arrays sample the data in
step. A programming interface configures the operation of the gate arrays. In
addition, each gate array device contains a diode in which the junction
temperature is monitored to ensure the module is being cooled properly.
Acquisition IC. Each acquisition circuit is made up of a single acquisition IC.
Each acquisition IC functions as a 17-channel state/timing logic analyzer. Two
acquisition ICs are included on every single logic analyzer card for a total of 32
data channels and 2 clock/data channels. All of the sequencing, storage
qualification, pattern/range recognition and even counting functions are
performed by the acquisition IC.
The acquisition ICs perform master clocking functions. The state acquisition
clock is sent to each acquisition IC, and the acquisition ICs generate their own
sample clock. Every time the user selects RUN, the acquisition ICs individually
perform a clock optimization before data is stored. Clock optimization involves
using programmable delays in the acquisition ICs to position the master sampling
clock transition where valid data is captured. This procedure reduces the effects
of channel-to-channel skew and other propagation delays.
In timing acquisition mode, a 100 MHz backplane clock from the logic analysis
system mainframe drives the sample rate of the acquisition ICs. A master
acquisition IC monitors the RUN signal asserted based on user input. The master
acquisition IC then gates the sample clocks to all other acquisition ICs in the
module.
Acquisition memory. The acquisition memory is a bank of 16-bit SDRAM
devices and stores the processed data from the acquisition IC. Acquisition
memory input/output is controlled by a memory controller, a bank of field
programmable gate arrays (FPGA). The memory controller is initialized when
power is applied to the logic analysis system from files stored on the system hard
disk drive. During normal operation of the module, then memory controller is
reprogrammed based on configuration of the module from user input. a second
initialization file is loaded into the memory controller when the performance
verification software is loaded into the system.