Specifications

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Chapter 5: Troubleshooting
Passing the System Clocks (Master/Slave/Psync) Test implies that the acquisition
ICs of each expander board of a multi-card configuration can properly receive
system clocks, and that all acquisition ICs in the multi-card module will properly
capture data.
Analyzer Memory Bus SU/H Measure. The Analyzer Memory Bus SU/H
Measure is an internal test that ensures the timing between the acquisition IC and
acquisition memory is within acceptable parameters.
System Backplane Clock Test. The System Backplane Clock Test verifies the
100 MHz acquisition system clock. The test also ensures an on-board phase-
locked loop can properly generate multiples of the acquisition system clock
frequency. The 100 MHz acquisition system clock is first routed directly to the
acquisition ICs. A timer is initialized, run, and stopped after 100ms. the counter is
read, and compared with a known value. The acquisition system clock is then
routed to the phase-locked loop to generate a frequency of 166.7 MHz. Again, the
counter is initialized, run, and stopped after 100ms. The counter is read, and
compared with a known value.
Passing the System Backplane Clock Test implies that the system acquisition
clock is operating, and is within 5% of the desired acquisition frequency.
Inter-chip Resource Bus Test. The Inter-chip Resource Bus Test verifies the
resource lines that run between each acquisition IC to ensure that the resource
lines can be both driven as outputs and read as inputs. The resource registers are
written with test patterns, read back, then compared with known values. The
resource registers are then written with test patterns, read back from a different
acquisition IC, and then compared with known values.
Inter-module Flag Bits Test. Flag bits are used for module-to-module
communication within the 16700-series system. The Inter-module Flag Bits Test
verifies that the flag bit lines can be driven and received by each acquisition IC in
each module. Test patterns are written to the flag registers, read by the other
acquisition ICs in the other modules, and then compared with known values.
Passing the Inter-module Flag Bits Test implies that the acquisition ICs can
communicate using Flag Bits through the CPU interface and the 16700-series
backplane, and that the operations utilizing the flag bits can be properly
recognized by all modules in the system.
Global and Local Arm Lines Test. The Global and Local Arm Lines Test
verifies that the local arm signal can be received by each acquisition IC on the
master board. The test also verifies the global arm signal can be driven by each
acquisition IC on a master board, and received by all acquisition ICs in the
module on the master and on all expander boards. The arm lines are asserted and
read at the acquisition ICs to ensure each acquisition IC recognizes the signal.
Passing the Global and Local Arm Lines Test implies any acquisition ICs on the