Specifications

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Chapter 5: Troubleshooting
Memory DMA Unload Test. The Memory DMA Unload Test performs the same
functions as the Memory Unload Test, except DMA backplane transfers are used
to read the data from acquisition memory.
Memory Sleep Mode Test. The Memory Sleep Mode Test verifies the self
refresh mode of acquisition memory devices. Memory self refresh mode is
enabled when the memory control device is reprogrammed during normal
operation.
Passing the Memory Sleep Mode Test verifies the acquisition memory will retain
data during changes in 16760A operating modes during normal operation.
HW Accelerated Search Test. The HW Accelerated Search Test verifies the
fundamental search capabilities of the module. Acquisition RAM is loaded with
test data, and the search registers in the gate arrays are programmed with test
patterns. Basic search functions including return and count pattern, are done and
monitored for success.
Passing the HW Accelerated Search Test implies that the module’s fundamental
Hardware accelerated pattern search capabilities are operating and that pattern
searches and pattern occurrence counts can be performed.
Chip Registers Read/Write Test. The Chip Registers Read/Write Test verifies
that the registers of each acquisition IC are operating properly. Test patterns are
written to each register on each acquisition IC, read, and compared with known
values. The registers are reset, and verified that each register has been initialized.
Test patterns are then written to ensure the chip address lines are not shorted or
opened. Finally test data is written to registers of individual acquisition ICs to
ensure each acquisition IC can be selected independently.
Passing the Chip Registers Read/Write Test implies that the acquisition IC
registers can store acquisition control data to properly manage the operating of
each IC.
Analyzer Chip Memory Bus Test. The Analyzer Chip Memory Bus Test
verifies the operation of the acquisition memory buses between acquisition ICs.
After initializing the memory a walking “1” and “0” pattern is created at the
output of the acquisition ICs. This test data is stored in memory, read, and
compared with known values.
Passing the Analyzer Chip Memory Bus Test implies that the acquisition memory
buses between the acquisition ICs and acquisition memory is operating, and that
acquisition data can propagate from the ICs to memory.
System Clocks (Master/Slave/Psync) Test. The System Clocks (Master/
Slave/Psync) Test verifies the system clock are functional between all boards in a
master/expander multi-card module. The module is configured for a simple
measurement and test data is created. The test data is then downloaded and
compared with known values.