Specifications

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Chapter 5: Troubleshooting
registers of the backplane interface device and the memory control device can be
written to then read. Both a walking “1” and “0” pattern is written to the device
registers. The registers are then read and compared with known values.
Passing the FPGA Registers Test implies that the module hardware configuration
can be properly managed as part of normal module operation.
Memory Data Bus Test. The Memory Data Bus Test verifies the read/write
access of the acquisition module from the system backplane. In addition, some of
the operations of the acquisition memory and control are also tested. A walking
“1” and “0” is written to the first memory location. The contents of the first
memory location is then downloaded and compared with known values.
Passing the Memory Data Bus Test implies that data stored in the acquisition
memory can be uploaded from the 16760A module to the 16700-series system.
Memory Address Bus Test. The Memory Address Bus Test verifies the
operation of the acquisition memory address bus. After initializing the acquisition
memory, the address bus is exercised with a walking “1” and “0” pattern. At each
resulting memory address, test data is stored. The test data is then downloaded
and compared with known values.
Passing the Memory Address Bus Test implies that each signal line of the
acquisition memory address bus is operational, and therefore all locations in the
acquisition memory can be accessed.
HW Assisted Memory Cell Test. After verifying the acquisition memory
address bus signal lines using the Memory Address Bus Test, the HW Assisted
Memory Cell Test does a read/write test on every location in the acquisition
memory. Each location in acquisition memory is filled with a test data pattern.
After loading acquisition memory, the test data at each memory location is
downloaded then compared with known values.
Passing the HW Assisted Memory Cell Test implies that each location in
acquisition memory can be accessed, written, read, and can properly store data.
Memory Unload Modes Test. The Memory Unload Modes Test verifies the
CPU interface can properly manage the acquisition memory unload in both full-
channel, half-channel, and interleaved modes. Test data is written to acquisition
memory. Different unload modes are selected, then the data is read and
compared with known values.
Passing the Memory Unload Modes Test implies that the data can be reliably read
from acquisition memory in full-channel, half-channel, or interleaved mode. This
test along with the Memory Data Bus Test and Memory Address Bus Test provide
complete testing of acquisition memory downloading through the CPU interface.