Service Guide Publication number 16760-97013 May 2004 For Safety and Regulatory information see the pages at the end of the book. © Copyright Agilent Technologies 2001-2004 All Rights Reserved.
The Agilent 16760A Logic Analyzer—At a Glance The Agilent Technologies 16760A is a 1500 Mb/s state, 800 MHz timing logic analyzer module for the Agilent Technologies 16700-series logic analysis system. The 16760A offers high performance measurement capability.
The 16760A uses operating system version A.02.20.00 or higher. Agilent Technologies 16700-series mainframes with serial number prefix lower than US4111 are factory-installed with older operating system versions. If your mainframe operating system is older than the required version, contact your Agilent Technologies Service Center for newer software. Refer to “Mainframe and Operating System” on page 10 for more information.
In This Book This book is the service guide for the 16760A 1500 Mb/s state, 800 MHz timing logic analyzer module. This service guide has eight chapters. Chapter 1, “General Information,” beginning on page 9 contains information about the module and includes accessories for the module, specifications and characteristics of the module, and a list of the equipment required for servicing the module. Chapter 2, “Preparing for Use,” beginning on page 15 tells how to prepare the module for use.
Contents 1 General Information Accessories 10 Mainframe and Operating System 10 Specifications 11 Characteristics 12 Environmental Characteristics 12 Recommended Test Equipment 13 2 Preparing for Use Power Requirements 16 Operating Environment 16 Storage 16 To inspect the module 16 To prepare the mainframe 17 To configure a one-card module 18 To configure a multi-card module 20 To install the module 26 To turn on the system 28 To test the module 28 To clean the module 29 3 Testing Performance To assemble
Contents Configure the logic analysis system 51 Adjust sampling positions using Eye Finder Re-aligning a stray channel 57 Test Pod 1 in 200 Mb/s mode 56 59 Determine PASS/FAIL (1 of 2 tests) 59 Open and configure the Listing window.
Contents Performance Test Record 96 4 Calibrating Calibration Strategy 100 5 Troubleshooting To use the flowcharts 102 To run the self-tests 105 Self-Test Descriptions 106 To exit the test system 112 To test the cables using an Agilent E5378A Single-ended Probe 113 To test the cables using an Agilent E5379A Differential Probe 121 6 Replacing Assemblies Tools Required 128 To remove the module 128 To remove the logic analyzer cable 130 To install the logic analyzer cable 131 To replace the circuit board
1 General Information This chapter lists the accessories, the specifications and characteristics, and the recommended test equipment.
Chapter 1: General Information Accessories One or more of the following accessories, not supplied, are required to operate the 16760A logic analyzer.
Chapter 1: General Information Specifications The specifications are the performance standards against which the product is tested. Setup/Hold Window: tWidth Individual Data Channel vHeight Data Eye tSetup tHold vThreshold 0V Sampling Position * User Adjustable tSample* Clock Channel 16760b05 Specifications for each input Minimum Parameter Data to Clock 1500 Mb/s 1250 Mb/s 800 Mb/s 400 Mb/s 200 Mb/s Description/Notes tWidth* 500 ps 1.
Chapter 1: General Information Characteristics The characteristics are not specifications, but are included as additional information. Threshold Accuracy ±(30 mV+1.
Chapter 1: General Information Recommended Test Equipment Equipment Required Equipment Critical Specifications Recommended Agilent Model/Part Use Probe Adapter no substitute E5378A P,T Probe Adapter (Qty 2)* no substitute E5382A P, T Ground Clips (Qty 10) no substitute 16517-82105 (pkg of 20) T Stimulus Board no substitute 16760-60001 T Pulse Generator 750 MHz, 666.6 ps pulse width, < 120 ps rise time 8133A Option 003 P,T Digitizing Oscilloscope ≥11 GHz bandwidth, <31.
Chapter 1: General Information 14
2 Preparing for Use This chapter gives you instructions for preparing the logic analyzer module for use.
Chapter 2: Preparing for Use Power Requirements All power supplies required for operating the logic analyzer are supplied through the backplane connector in the mainframe. Operating Environment The operating environment is listed on page 12. Note the non-condensing humidity limitation. Condensation within the instrument can cause poor operation or malfunction. Provide protection against internal condensation.
Chapter 2: Preparing for Use mechanical defects. If you find any defects, contact your nearest Agilent Technologies Sales Office. Arrangements for repair or replacement are made, at Agilent Technologies' option, without waiting for a claim settlement. To prepare the mainframe CAUTION: Turn off the mainframe power before removing, replacing, or installing the module. CAUTION: Electrostatic discharge can damage electronic components.
Chapter 2: Preparing for Use 4 Starting from the top, pull the cards and filler panels that need to be moved halfway out. CAUTION: All multi-card modules will be cabled together. Pull these cards out together. 5 Remove the cards and filler panels. Remove the cards or filler panels that are in the slots intended for the module installation. Push all other cards into the card cage, but not completely in. This is to get them out of the way for installing the module.
Chapter 2: Preparing for Use CAUTION: If you pull on the flexible ribbon part of the 2x10 cable, you might damage the cable assembly. Using your thumb and finger, grasp the ends of the cable connector. Apply pressure to the ends of the cable connector to disengage the metal locking tabs of the connector from the cable socket on the board. Then pull the connector from the cable socket. NOTE: Save unused cables for future configurations.
Chapter 2: Preparing for Use To configure a multi-card module 1 Plan the configuration. Multicard modules can only be connected as shown in the illustration. Expander cards are evenly distributed above and below the master card. Select the card that will be the master card, and set the remaining cards aside. 2 Obtain two 2x40 cables from the accessory pouch for every expander card being configured.
Chapter 2: Preparing for Use 3 Connect a 2x40 cable to J9 and to J10 of each card in the multicard configuration. 4 On the expander cards, disconnect the end of the 2x10 cable that is plugged into the connector labeled "Master." CAUTION: If you pull on the flexible ribbon part of the 2x10 cable, you might damage the cable assembly. Using your thumb and finger, grasp the ends of the cable connector.
Chapter 2: Preparing for Use 5 Begin stacking the cards together according to the drawing under step 1. While stacking, connect the free end of the 2x40 cable on the lower card J9 to J500 of the upper card, on the underside of the card. Connect the free end of the 2x40 cable on the lower card J10 to J501 of the upper card, on the underside of the card. NOTE: These instructions show a five-card set. If you are planning a set of less than five cards, see the diagram on page 20 for correct placement.
Chapter 2: Preparing for Use 6 Feed the free end of the 2x10 cables of the lower expander cards through the access holes to the master card. Plug the 2x10 cables into J4 (bottommost expander in a five-card configuration) and J5 (expander that is next to the master card) on the master card.
Chapter 2: Preparing for Use 7 Stack the remaining expander boards on top of the master board. While stacking, connect the free end of the 2x40 cables on the lower card J10 and J9 to the upper card J501 and J500.
Chapter 2: Preparing for Use 8 Feed the free end of the 2x10 cables of the expander cards through the access holes to the master card. Plug the 2x10 cables into J7 (expander that is next to the master card) and J8 (top-most expander in a four- or five-card configuration) on the master card.
Chapter 2: Preparing for Use To install the module 1 Slide the cards above the slots for the module about halfway out of the mainframe. 2 With the probe cables facing away from the instrument, slide the module approximately halfway into the mainframe. 3 Slide the complete module into the mainframe, but not completely in. Each card in the instrument is firmly seated and tightened one at a time in step 5. 4 Position all cards and filler panels so that the endplates overlap.
Chapter 2: Preparing for Use 5 Seat the cards and tighten the thumbscrews. Starting with the bottom card, firmly seat the cards into the backplane connector of the mainframe. Keep applying pressure to the center of the card endplate while tightening the thumbscrews finger-tight. Repeat this for all cards and filler panels starting at the bottom and moving to the top. CAUTION: Correct air circulation keeps the instrument from overheating.
Chapter 2: Preparing for Use To turn on the system 1 Connect the power cable to the mainframe. 2 Turn on the instrument power switch. When you turn on the instrument power switch, the instrument performs powerup tests that check mainframe circuitry. After the powerup tests are complete, the screen will look similar to the sample screen below. To test the module The logic analyzer module does not require an operational accuracy calibration or adjustment.
Chapter 2: Preparing for Use To clean the module • With the mainframe turned off and unplugged, use a cloth moistened with a mixture of mild detergent and water to clean the rear panel. • Do not attempt to clean the module circuit board.
Chapter 2: Preparing for Use 30
3 Testing Performance This chapter tells you how to test the performance of the logic analyzer against the specifications.
Chapter 3: Testing Performance To ensure the logic analyzer is operating as specified, software tests (self-tests) and manual performance tests are done. The logic analyzer is considered performance-verified if all of the software tests and manual performance tests have passed. The procedures in this chapter indicate what constitutes a “Pass” status for each of the tests. Test Strategy This chapter shows the module being tested in an Agilent Technologies 16700Bseries mainframe.
Chapter 3: Testing Performance Test Equipment Each procedure lists the recommended test equipment. You can use equipment that satisfies the specifications given. However, the procedures are based on using the recommended model or part number. Instrument Warm-Up Before testing the performance of the module, warm-up the instrument and the test equipment for 30 minutes.
Chapter 3: Testing Performance To assemble the SMA/Flying Lead test connectors To assemble the SMA/Flying Lead test connectors The SMA/Flying Lead test connectors provide a high-bandwidth connection between the logic analyzer and the test equipment. The following procedure explains how to fabricate the four required test connectors. Materials Required Material Critical Specification SMA Board Mount Connector (Qty 8) Recommended Model/Part Johnson 142-0701-801 (ref: www.johnsoncomponents.
Chapter 3: Testing Performance To assemble the SMA/Flying Lead test connectors b Trim about 1.5 mm from the pin strip inner leads and straighten them so that they touch the outer leads. c Trim about 2.5 mm from the outer leads. solder d Using a very small amount of solder, tack each inner lead to each outer lead at the point where they are touching.
Chapter 3: Testing Performance To assemble the SMA/Flying Lead test connectors 2 Solder the pin strip to the SMA board mount connector: a Solder the leads on the left side of the pin strip to the center conductor of the SMA connector as shown in the diagram below. b Solder the leads on the right side of the pin strip to the inside of the SMA connector’s frame as shown in the diagram below. Use a small amount of solder.
Chapter 3: Testing Performance To assemble the SMA/Flying Lead test connectors 4 Check your work: a Ensure that the following four points have continuity between them: The two pins on the left side of the pin strip, and the center conductors of each SMA connector. b Ensure that there is continuity between each of the two pins on the right side of the pin strip, and the SMA connector frames. c Ensure that there is NO continuity between the SMA connector center conductor and the SMA connector frame (ground).
Chapter 3: Testing Performance 16760A Minimum Data Eye Width and Minimum Clock Interval Performance Test Procedure 16760A Minimum Data Eye Width and Minimum Clock Interval Performance Test Procedure The specifications for the 16760A logic analyzer define a minimum data eye width and a minimum clock interval at which data can be acquired. Acquisition Mode: 200 Mb/s 400 Mb/s 800 Mb/s 1.25 Gb/s 1.5 Gb/s Minimum clock interval, active edge to active edge 5 ns 2.5 ns 1.
Chapter 3: Testing Performance Equipment Required Equipment Required The following equipment is required for the performance test procedure. Equipment Required Equipment Critical Specification Pulse Generator ≥ 765 MHz, two channels, differential Agilent or HP 8133A option 003 outputs, 150-180 ps rise/fall time (if faster, use transition time converters). 150 ps Transition Time Converter Required if pulse generator’s rise time is (Qty 4) less than 150 ps.
Chapter 3: Testing Performance Prepare the logic analysis system for testing Prepare the logic analysis system for testing 1 Turn on the logic analysis system. a Connect the keyboard and monitor to the rear panel of the logic analysis mainframe (16700B only). b Connect the mouse to the rear panel of the mainframe. c Plug in the power cord to the power connector on the rear panel of the mainframe. d Turn on the main power switch on the mainframe front panel.
Chapter 3: Testing Performance Prepare the logic analysis system for testing Some system CPU board tests may return a status of Untested because they require user action. Procedures to do these tests are found in the Agilent Technologies 16700B-series Logic Analysis System Service Guide. For the purposes of testing the Agilent 16760A module performance, running untested system CPU board tests are not required. If these tests are not done, the Agilent 16760A performance test is not affected.
Chapter 3: Testing Performance Initialize the test equipment for minimum data eye width/minimum clock interval test Initialize the test equipment for minimum data eye width/minimum clock interval test 1 Turn on the required test equipment. Let all of the test equipment and the logic analyzer warm up for 30 minutes before beginning any test. 2 Set up the pulse generator. a Set the frequency of the pulse generator. We will test in the 200 Mb/s mode first.
Chapter 3: Testing Performance Initialize the test equipment for minimum data eye width/minimum clock interval test 3 Set up the oscilloscope. a Set up the oscilloscope according to the following tables. Oscilloscope Setup Setup: Channel 1 Setup: Ch. 1 Probe Setup: Channel 2 On Attenuation: 1.00:1 On Attenuation: 1.
Chapter 3: Testing Performance Connect the test equipment for the minimum clock interval/minimum eye width test Connect the test equipment for the minimum clock interval/minimum eye width test Connect the 16760A Logic Analyzer Pod to the 8133A Pulse Generator 1 Connect a Transition Time Converter (if required—see page 39) to each of the four outputs of the 8133A pulse generator: Channel 1 OUTPUT, Channel 1 OUTPUT, Channel 2 OUTPUT, Channel 2 OUTPUT.
Chapter 3: Testing Performance Connect the test equipment for the minimum clock interval/minimum eye width test NOTE: Be sure to use the black ground clip (supplied with the E5382A Flying Lead Probe Set) and orient the leads so that the black clip is connected to one of the SMA/Flying Lead connector’s ground pins! 6 Connect the E5382A Flying Lead Probe Set’s CLK lead to the SMA/Flying Lead connector at the 8133A pulse generator’s Channel 1 OUTPUT.
Chapter 3: Testing Performance Set up the test equipment Set up the test equipment Next, verify and adjust the pulse generator’s DC offset, deskew the oscilloscope, and measure and adjust the pulse width. Verify and adjust 8133A pulse generator DC offset 1 On the 54845A oscilloscope, select Measure from the menu bar at the top of the display. 2 Select Markers... 3 In the Markers Setup window set marker “Ay” to 0.875 V, and set marker “By” to 1.125 V. 4 Observe the waveforms on the oscilloscope display.
Chapter 3: Testing Performance Set up the test equipment Deskew the oscilloscope This procedure neutralizes any skew in the oscilloscope’s waveform display. 1 On the 54845A oscilloscope, change the Horizontal scale from 500 ps/div to 200 ps/div. You can do this using the large knob in the Horizontal setup section of the front panel. 2 Select Setup from the menu bar at the top of the oscilloscope display. 3 Select Channel 1. 4 Select Probes.
Chapter 3: Testing Performance Set up the test equipment horizontal center of the graticule line is at 1 volt because the vertical offset was set to 1 volt in the oscilloscope setup described on page 43. 6 Select Close in the Probe Setup window. 7 Select Close in the Channel Setup window. Adjust the measured pulse width to 1.5 ns The pulse generator’s pulse width was set to 1.5 ns (in the setup on page 42).
Chapter 3: Testing Performance Set up the test equipment is ±((0.007% * ∆t) + (full scale/2x memory depth) + 30 ps) ≅ ±30 ps. Add 5 ps for display resolution. Add 35 ps test margin. 1500 ps - 30.15 ps - 5 ps - 35 ps = 1430 ps. Set the pulse width as measured on the 54845A/B oscilloscope to 1430 ps. On the oscilloscope move the Ax and Bx markers to the crossing points of the pulse and the horizontal center line. Read the pulse width at the bottom of the oscilloscope display. It is displayed as “∆=”.
Chapter 3: Testing Performance Configure the logic analysis system Configure the logic analysis system 1 Configure the Sampling settings. a In the Agilent 16700-series logic analysis system’s System window, select the 16760A logic analyzer icon, then select “Setup and Trigger”. A Setup and Trigger window will appear. b In the logic analyzer Setup and Trigger window, select the Sampling tab (if it is not already selected). c Under the Sampling tab, select State Mode.
Chapter 3: Testing Performance Configure the logic analysis system e Select the Count field, then select Off. 3 Configure the Format settings. a In the logic analyzer Setup and Trigger window, select the Format tab. b Under the Format tab, select Pod Assignment. c In the Pod Assignment window, use the mouse to drag the pod from the Unassigned Pods column to the Analyzer 1 column. d Select Close to close the Pod Assignment window.
Chapter 3: Testing Performance Configure the logic analysis system see the fields for Pod 1. channel assignment field scroll bar f Select the channel assignment field for the pod being tested, then select Individual in the pop-up menu. g Using the mouse, select each asterisk to un-assign all data channels on the pod. Ensure all channels are un-assigned on all pods. Now assign channels 2, 6, 10, and 14 for the pod being tested (Pod 1). An asterisk (*) means that a channel is assigned.
Chapter 3: Testing Performance Configure the logic analysis system a Select the pod threshold field for the pod that you are going to test. The Pod threshold window will appear. You must have the E5382A Flying Lead Probe attached to the pod you will be testing so that the pod threshold dialog will appear when you select the pod threshold field. pod threshold field b In the Pod threshold window, select User Defined and set the threshold value to 1 volt.
Chapter 3: Testing Performance Configure the logic analysis system scroll to the left and select “Clk Thresh...”. clock threshold button scroll bar e In the Clock Thresholds window, select the J clock threshold button, then in the J threshold window select Differential. f Select Close to close the J threshold window. Select Close to close the Clock Thresholds window. 5 Configure the Trigger settings.
Chapter 3: Testing Performance Configure the logic analysis system d Enter “A” in the “Label 1 =” field. Adjust sampling positions using Eye Finder 1 In the Setup and Trigger window, select the Sampling tab, then select the “Sampling Positions...” button (which is in the Clock Setup area of the window). The Eye Finder window will appear. Ensure that the “Sampling Positions” tab is selected. 2 From the menu bar in the Eye Finder window, select Results.
Chapter 3: Testing Performance Configure the logic analysis system move it to the recommended starting position of 0.6 ns. All of the blue bars will follow. 8 Select Run Eye Finder (the large green bar). 9 Ensure that an eye appears for each bit near the recommended starting position. Depending on your test setup, the eye position may vary. Any skew between channel 1 and channel 2 of your pulse generator will cause the eye position to shift to the left or right in the Eye Finder display.
Chapter 3: Testing Performance Configure the logic analysis system analyzer in the 1500 Mb/s mode.) 1 Using the mouse, drag the sample position (blue line) of a stray channel so that it is in the same eye as the other channels (drag channel Label1 [2] in the above example). The Suggested Position from Eye Finder (green triangle) will also move to the new eye. 2 Repeat the above step for all remaining stray channels. 3 Select Run Eye Finder.
Chapter 3: Testing Performance Test Pod 1 in 200 Mb/s mode Test Pod 1 in 200 Mb/s mode The steps that follow include pass/fail criteria. Determine PASS/FAIL (1 of 2 tests) 1 PASS/FAIL: If an eye exists near the recommended starting position for every bit, and Eye Finder places a blue bar in the eye for each bit, then the logic analyzer passes this portion of the test.
Chapter 3: Testing Performance Test Pod 1 in 200 Mb/s mode b In the Listing window, select the Markers tab. c Select the G1: button and the Markers Setup window will appear. d Select the field immediately to the right of G1, and select Pattern. e Select the field immediately to the right of G2, and select Pattern. f Right-click on the Interval field (which is below G1 and G2) and select Delete. g Select the field immediately to the right of “Data at” and select Beginning.
Chapter 3: Testing Performance Test Pod 1 in 200 Mb/s mode b Select OK to close the error message window. c In the Marker Setup window, select the G1 Define... button. The “Marker Pattern for ” window will appear. In the pattern field, enter "a", then select Close. d In the Marker Setup window, select the G2 Define... button. The G2 Marker Pattern window will appear. In the pattern field, enter "5", then select Close.
Chapter 3: Testing Performance Test Pod 1 in 200 Mb/s mode for marker...”. 1 Let the logic analyzer run repetitive for about 1 minute. If no error message is displayed the test passes. If the red error window “Error- Listing <1> Pattern NOT found...” appears during the minute or so that it runs repetitively, then the logic analyzer fails the test. Record the failure in the appropriate place on the test record.
Chapter 3: Testing Performance Test Pod 1 in 200 Mb/s mode NOTE: As a point of curiosity, you may want to determine the absolute minimum pulse width and/or absolute maximum frequency at which data can be acquired. The “Performance Test Record” on page 95 does not include places for recording these values because the Performance Verification procedure only verifies that the logic analyzer meets specifications.
Chapter 3: Testing Performance Test Pod 1 in 200 Mb/s mode See page 48 for details. 6 Adjust the sampling positions (run Eye Finder). See page 55. 7 Determine pass or fail (1 of 2 tests). See page 58. 8 Ensure that the Listing window is set up. See page 58. 9 Select the Run Repetitive icon in the Listing window. 10 Determine pass or fail (2 of 2 tests). See page 60.
Chapter 3: Testing Performance Test Pod 2 in 200 Mb/s mode Test Pod 2 in 200 Mb/s mode 1 Leave the first E5382A Flying Lead Probe Set connected to Pod 1 of the logic analyzer. Remove the Pod 1 flying leads 2, 6, 10, and 14 from the SMA/Flying Lead test connectors. Do not remove the flying leads that are connected to CLK and CLK. 2 Connect the second E5382A Flying Lead Probe Set to Pod 2 of the logic analyzer.
Chapter 3: Testing Performance Test Pod 2 in 200 Mb/s mode and the Trigger Functions subtab. b Select “Find pattern n times” and select the “Replace” button. c Enter “A” in the “Label 1 = “ field. 15 Adjust the sampling positions using Eye Finder. Be sure to expand “Label1 (4 channels)” and use the recommended starting position noted on page 56. Realign any stray channels if necessary. See page 56. 16 Determine pass or fail (1 of 2 tests). See page 58. 17 Ensure that the Listing window is set up.
Chapter 3: Testing Performance Test Pod 1 in the 400 Mb/s mode Test Pod 1 in the 400 Mb/s mode 1 Disconnect the Pod 2 E5382A Flying Lead Probe Set’s bits 2, 6, 10, and 14 from the SMA/Flying Lead test connectors’ pin strip connectors. The original E5382A Flying Lead Probe Set should still be connected to Pod 1. The J clock on Pod 1 will be used for all tests.
Chapter 3: Testing Performance Test Pod 1 in the 400 Mb/s mode pod 2 bits. 12 Assign bits 2, 6, 10, and 14 of Pod 1. 13 Ensure that the Pod 1 threshold is set to 1 volt. See page 53. 14 In the “Setup and Trigger...” window, Format tab, ensure that the J clock threshold is still set to Differential. 15 Re-establish the trigger function: a In the logic analyzer’s Setup and Trigger window, select the Trigger tab, and the Trigger Functions subtab.
Chapter 3: Testing Performance Test Pod 1 in the 400 Mb/s mode page 56. 20 In the “Setup and Trigger...” window, Clock Setup area, set the clock mode to “Both Edges.” 21 In the Eye Finder window, align the blue bars vertically. See page 55. 22 Grab the blue bar for “Label1 (4 Channels)” and move it to the recommended starting position you noted in the prior step. 23 Run Eye Finder again. Some eyes may close, but the eyes in the sampling position you chose on page 67 should remain open.
Chapter 3: Testing Performance Test Pod 1 in the 400 Mb/s mode 24 Perform the procedure “Determine PASS/FAIL (1 of 2 tests)” on page 58. 25 Select the Run Repetitive icon in the Listing window. 26 Perform the procedure “Determine PASS/FAIL (2 of 2 tests)” on page 60. Test the complement of the bits (Pod 1, 400 Mb/s mode) Now test the logic analyzer using complement data. 1 On the 8133A pulse generator, in the PULSE setup for CHANNEL 2, select COMP. 2 Note that the signal on the oscilloscope has moved.
Chapter 3: Testing Performance Test Pod 2 in 400 Mb/s mode Test Pod 2 in 400 Mb/s mode 1 Leave the first E5382A Flying Lead Probe Set connected to Pod 1 of the logic analyzer. Remove the Pod 1 flying leads 2, 6, 10, and 14 from the SMA/Flying Lead test connectors. Do not remove the flying leads that are connected to CLK and CLK flying leads.
Chapter 3: Testing Performance Test Pod 2 in 400 Mb/s mode c Enter “A” in the “Label 1 = “ field. 14 Adjust the sampling positions using Eye Finder. Be sure to expand “Label1 (4 channels)”. Use the starting position you noted on page 67. Realign any stray channels if necessary. See page 56. 15 Determine pass or fail (1 of 2 tests). See page 58. 16 Ensure that the Listing window is set up. See page 58. 17 Select the Run Repetitive icon in the Listing window. 18 Determine pass or fail (2 of 2 tests).
Chapter 3: Testing Performance Test Pod 1 in the 800 Mb/s mode Test Pod 1 in the 800 Mb/s mode 1 Disconnect the Pod 2 E5382A Flying Lead Probe Set’s bits 2, 6, 10, and 14 from the SMA/Flying Lead test connectors’ pin strip connectors. The original E5382A Flying Lead Probe Set should still be connected to Pod 1. The J clock on Pod 1 will be used for all tests.
Chapter 3: Testing Performance Test Pod 1 in the 800 Mb/s mode width of the 8133A pulse generator so that the pulse width measured at 1 volt on the oscilloscope is equal to 750 ps minus the measurement uncertainty and display resolution of the oscilloscope, further reduced by 35 ps for test margin. If you are using the 54845A/B oscilloscope, the measurement uncertainty is ±((0.007% * ∆t) + (full scale/2x memory depth) + 30 ps) ≅ ±30 ps. Add 5 ps for display resolution. Add 35 ps test margin.
Chapter 3: Testing Performance Test Pod 1 in the 800 Mb/s mode mode. 11 In the “Setup and Trigger...” window, Sampling tab, Clock Setup area, set the clock mode to “Rising Edge”. 12 In the logic analyzer’s Setup and Trigger window, Format tab, unassign all pod 2 bits. 13 Assign bits 2, 6, 10, and 14 of Pod 1. 14 Ensure that the Pod 1 threshold is set to 1 volt. See page 53. 15 In the “Setup and Trigger...” window, Format tab, ensure that the J clock threshold is still set to Differential.
Chapter 3: Testing Performance Test Pod 1 in the 800 Mb/s mode different based on your test setup. Bring stray channels into alignment if necessary. See page 56. 20 In the “Setup and Trigger...” window, Clock Setup area, set the clock mode to “Both Edges.” 21 In the Eye Finder window, align the blue bars vertically. See page 55. 22 Grab the blue bar for “Label1 (4 Channels)” and move it to the recommended starting position you noted in the prior step. 23 Run Eye Finder again.
Chapter 3: Testing Performance Test Pod 1 in the 800 Mb/s mode position you chose on page 74 should remain open. 24 Perform the procedure “Determine PASS/FAIL (1 of 2 tests)” on page 58. 25 Select the Run Repetitive icon in the Listing window. 26 Perform the procedure “Determine PASS/FAIL (2 of 2 tests)” on page 60. Test the complement of the bits (Pod 1, 800 Mb/s mode) Now test the logic analyzer using complement data. 1 On the 8133A pulse generator, in the PULSE setup for CHANNEL 2, select COMP.
Chapter 3: Testing Performance Test Pod 1 in the 800 Mb/s mode 8 Select the Run Repetitive icon in the Listing window.
Chapter 3: Testing Performance Test Pod 2 in 800 Mb/s mode Test Pod 2 in 800 Mb/s mode 1 Leave the first E5382A Flying Lead Probe Set connected to Pod 1 of the logic analyzer. Remove the Pod 1 flying leads 2, 6, 10, and 14 from the SMA/Flying Lead test connectors. Do not remove the flying leads that are connected to CLK and CLK flying leads.
Chapter 3: Testing Performance Test Pod 2 in 800 Mb/s mode c Enter “A” in the “Label 1 = “ field. 14 Adjust the sampling positions using Eye Finder. Be sure to expand “Label1 (4 channels)”. You can use the starting position you noted on page 74. Bring stray channels into alignment if necessary. See page 56. 15 Determine pass or fail (1 of 2 tests). See page 58. 16 Ensure that the Listing window is set up. See page 58. 17 Select the Run Repetitive icon in the Listing window.
Chapter 3: Testing Performance Test Pod 1 in the 1250 Mb/s mode Test Pod 1 in the 1250 Mb/s mode 1 Disconnect the Pod 2 E5382A Flying Lead Probe Set’s bits 2, 6, 10, and 14 from the SMA/Flying Lead test connectors’ pin strip connectors. The original E5382A Flying Lead Probe Set should still be connected to Pod 1. The J clock on Pod 1 will be used for all tests.
Chapter 3: Testing Performance Test Pod 1 in the 1250 Mb/s mode tab. In the “State Mode Controls” section, select the “1250 Mb/s / 128M Half Chan” mode. The clock mode will change to “Both Edges”. 11 In the logic analyzer’s Setup and Trigger window, Format tab, unassign all pod 2 bits. The channel assignment dialog looks different in half-channel mode because only half of the channels can be assigned now. 12 Assign bits 2, 6, 10, and 14 of Pod 1. 13 Verify that the Pod 1 threshold is set to 1 volt.
Chapter 3: Testing Performance Test Pod 1 in the 1250 Mb/s mode necessary. See page 56. 20 Re-set the pulse generator frequency to 625 MHz plus the test margin (638 MHz). 21 In the Eye Finder window, align the blue bars vertically. See page 55. 22 Grab the blue bar for “Label1 (4 Channels)” and move it to the recommended starting position you noted in the prior step. 23 Run Eye Finder again. Some eyes may close, but the eyes in the sampling position you chose on page 81 should remain open.
Chapter 3: Testing Performance Test Pod 1 in the 1250 Mb/s mode 24 Perform the procedure “Determine PASS/FAIL (1 of 2 tests)” on page 58. 25 Select the Run Repetitive icon in the Listing window. 26 Perform the procedure “Determine PASS/FAIL (2 of 2 tests)” on page 60. Test the complement of the bits (Pod 1, 1250 Mb/s mode) Now test the logic analyzer using complement data. 1 On the 8133A pulse generator, in the PULSE setup for CHANNEL 2, select COMP. 2 Note that the signal on the oscilloscope has moved.
Chapter 3: Testing Performance Test Pod 2 in 1250 Mb/s mode Test Pod 2 in 1250 Mb/s mode 1 Leave the first E5382A Flying Lead Probe Set connected to Pod 1 of the logic analyzer. Remove the Pod 1 flying leads 2, 6, 10, and 14 from the SMA/Flying Lead test connectors. Do not remove the flying leads that are connected to CLK and CLK flying leads.
Chapter 3: Testing Performance Test Pod 2 in 1250 Mb/s mode c Enter “A” in the “Label 1 = “ field. 14 Adjust the sampling positions using Eye Finder. Be sure to expand “Label1 (4 channels)”. You can use the starting position you noted on page 81. Realign any stray channels if necessary. See page 56. 15 Determine pass or fail (1 of 2 tests). See page 58. 16 Ensure that the Listing window is set up. See page 58. 17 Select the Run Repetitive icon in the Listing window.
Chapter 3: Testing Performance Test Pod 1 in the 1500 Mb/s mode Test Pod 1 in the 1500 Mb/s mode 1 Disconnect the Pod 2 E5382A Flying Lead Probe Set’s bits 2, 6, 10, and 14 from the SMA/Flying Lead test connectors’ pin strip connectors. The original E5382A Flying Lead Probe Set should still be connected to Pod 1. The J clock on Pod 1 will be used for all tests.
Chapter 3: Testing Performance Test Pod 1 in the 1500 Mb/s mode Adjust the measured pulse width to 600 ps In this procedure, you will use the oscilloscope’s measurement markers to measure the actual pulse width in the test setup. Then you will adjust the pulse generator so that the measured pulse width is as specified. 9 Observe the 54845A oscilloscope display.
Chapter 3: Testing Performance Test Pod 1 in the 1500 Mb/s mode bottom of the oscilloscope display. It is displayed as “∆=”. 10 In the logic analyzer “Setup and Trigger...” window, select the Sampling tab. In the “State Mode Controls” section, select the “1500 Mb/s / 128M Half Chan” mode. 11 In the logic analyzer’s Setup and Trigger window, Format tab, unassign all pod 2 bits. 12 Assign bits 2, 6, 10, and 14 of Pod 1. 13 Ensure that the Pod 1 threshold is set to 1 volt. See page 53.
Chapter 3: Testing Performance Test Pod 1 in the 1500 Mb/s mode Determine and set Eye Finder Position (1500 Mb/s mode) 16 Set the pulse generator frequency to half of the required value. If it was set to 765 MHz, then temporarily set it to 383 MHz. 17 In the Eye Finder (Sampling Positions) window, expand “Label1 (4 channels)”. 18 Grab the blue bar for “Label1 (4 Channels)” and move it to approximately 3.1 ns. All blue bars will follow.
Chapter 3: Testing Performance Test Pod 1 in the 1500 Mb/s mode if necessary. See page 56. 24 Perform the procedure “Determine PASS/FAIL (1 of 2 tests)” on page 58. 25 Select the Run Repetitive icon in the Listing window. 26 Perform the procedure “Determine PASS/FAIL (2 of 2 tests)” on page 60. Test the complement of the bits (Pod 1, 1500 Mb/s mode) Now test the logic analyzer using complement data. 1 On the 8133A pulse generator, in the PULSE setup for CHANNEL 2, select COMP.
Chapter 3: Testing Performance Test Pod 1 in the 1500 Mb/s mode 9 Perform the procedure “Determine PASS/FAIL (2 of 2 tests)” on page 60 91
Chapter 3: Testing Performance Test Pod 2 in 1500 Mb/s mode Test Pod 2 in 1500 Mb/s mode 1 Leave the first E5382A Flying Lead Probe Set connected to Pod 1 of the logic analyzer. Remove the Pod 1 flying leads 2, 6, 10, and 14 from the SMA/Flying Lead test connectors. Do not remove the flying leads that are connected to CLK and CLK flying leads.
Chapter 3: Testing Performance Test Pod 2 in 1500 Mb/s mode c Enter “A” in the “Label 1 = “ field. 14 Adjust the sampling positions using Eye Finder. Be sure to expand “Label1 (4 channels)”. You can use the starting position you noted on page 89. Realign any stray channels if necessary. See page 56. 15 Determine pass or fail (1 of 2 tests). See page 58. 16 Ensure that the Listing window is set up. See page 58. 17 Select the Run Repetitive icon in the Listing window.
Chapter 3: Testing Performance To test the multi-card module To test the multi-card module This section applies when cards were received as a multi-card module, and you have reconfigured them as single card modules for testing. All single card modules must be reconfigured into their original multicard module configuration upon completion of the “16760A Minimum Data Eye Width and Minimum Clock Interval Performance Test Procedure”.
Chapter 3: Testing Performance Performance Test Record Performance Test Record Performance Test Record 16760A Logic Analyzer Logic Analyzer Serial No. Work Order No. Date: Recommended Test Interval - 2 Year/4000 hours Recommended next testing: Test Equipment Used Pulse Generator Model No. Oscilloscope Model No. Pulse Generator Serial No. Oscilloscope Serial No.
Chapter 3: Testing Performance Performance Test Record 96
4 Calibrating This chapter gives you instructions for calibrating the logic analyzer.
Chapter 4: Calibrating Calibration Strategy The 16760A logic analyzer does not require an operational accuracy calibration. To test the module against the module specifications, refer to Chapter 3, “Testing Performance,” beginning on page 31.
5 Troubleshooting This chapter helps you troubleshoot the module to find defective assemblies.
Chapter 5: Troubleshooting The troubleshooting consists of flowcharts, self-test instructions, a cable test, and a test for the auxiliary power supplied by the probe cable. If you suspect a problem, start at the top of the first flowchart. During the troubleshooting instructions, the flowcharts will direct you to perform the selftests or the cable test. The service strategy for this instrument is the replacement of defective assemblies.
Chapter 5: Troubleshooting Troubleshooting Flowchart 1 103
Chapter 5: Troubleshooting Troubleshooting Flowchart 2 104
Chapter 5: Troubleshooting To run the self-tests Self-tests identify the correct operation of major, functional subsystems of the module. You can run all self-tests without accessing the module. If a self-test fails, the troubleshooting flowcharts instruct you to change a part of the module. To run the self-tests: 1 In the System window, select the System Administration icon. 2 In the System Administration window, select the Admin tab, then select Self-Test. At the Test Query window, select Yes.
Chapter 5: Troubleshooting Self-Test Descriptions The self-tests for the logic analyzer identify the correct operation of major functional areas in the module. CPLD Register Test. The CPLD Register Test verifies that the 16700-series backplane can communicate with the 16760A module CPLD. The CPLD is used to configure the backplane and the memory devices. The test is done using both a walking “1” and walking “0” pattern. After the pattern has been stepped, internal device registers are read.
Chapter 5: Troubleshooting registers of the backplane interface device and the memory control device can be written to then read. Both a walking “1” and “0” pattern is written to the device registers. The registers are then read and compared with known values. Passing the FPGA Registers Test implies that the module hardware configuration can be properly managed as part of normal module operation. Memory Data Bus Test.
Chapter 5: Troubleshooting Memory DMA Unload Test. The Memory DMA Unload Test performs the same functions as the Memory Unload Test, except DMA backplane transfers are used to read the data from acquisition memory. Memory Sleep Mode Test. The Memory Sleep Mode Test verifies the self refresh mode of acquisition memory devices. Memory self refresh mode is enabled when the memory control device is reprogrammed during normal operation.
Chapter 5: Troubleshooting Passing the System Clocks (Master/Slave/Psync) Test implies that the acquisition ICs of each expander board of a multi-card configuration can properly receive system clocks, and that all acquisition ICs in the multi-card module will properly capture data. Analyzer Memory Bus SU/H Measure. The Analyzer Memory Bus SU/H Measure is an internal test that ensures the timing between the acquisition IC and acquisition memory is within acceptable parameters. System Backplane Clock Test.
Chapter 5: Troubleshooting master board can arm the module, and that all acquisition ICs can recognize the arm signal. EEPROM Test. The EEPROM Test verifies the operation of the module EEPROM, which stores the operational accuracy calibration factors. The existing contents of the EEPROM are uploaded into system memory. The EEPROM is overwritten with test patterns to verify that each cell in the EEPROM can independently store a 1 or 0.
Chapter 5: Troubleshooting Data Path Pass-Thru Test. The Data Path Pass-Thru Test ensures that incoming data can flow correctly between the comparators and the acquisition ICs. The gate arrays are programmed for low-speed acquisition, which makes them invisible to data. The comparators are configured in test mode to drive a toggling signal on one of the comparator outputs while all other outputs are held quiet.
Chapter 5: Troubleshooting acquisition ICs can reliably capture the incoming data. To exit the test system 1 Select Close to close any module or system test windows. 2 In the Self Test window, select Quit. 3 In the session manager window, select Start Session to launch a new logic analyzer session.
Chapter 5: Troubleshooting To test the cables using an Agilent E5378A Single-ended Probe This test allows you to functionally verify the logic analyzer cable and an Agilent E5378A probe. Equipment Required Equipment Critical Specification Recommended Part Stimulus Board No Substitute 16760-60001 1 Connect the logic analyzer to the stimulus board. a Connect an Agilent E5378A 100-pin single-ended probe to the logic analyzer module. Connect logic analyzer Pod 1 to the probe output marked “Odd.
Chapter 5: Troubleshooting should illuminate showing that the stimulus board is active 2 Set up the stimulus board. a Configure the oscillator select switch S1 according to the following settings: • S1 Off • S2 Off • S3 Off • Int b Configure the data mode switch S4 according to the following settings: • Even • Count c Press the Resynch VCO button, then Counter RST (Counter Reset) button. 3 Set up the logic analyzer a Open the Session Manager window and select “Start Session.
Chapter 5: Troubleshooting Setup and Trigger. A Setup and Trigger window appears. c In the logic analysis system window, select the module icon, then select Listing. A Listing window appears. 4 Set up the Sampling tab a In the logic analyzer Setup and Trigger window, select the Sampling tab. b Under the Sampling tab, select State Mode. c Select the clock edge field for J-clock, then select Rising Edge.
Chapter 5: Troubleshooting e Select the Count field, then select Off. 6 Configure the Format tab a In the logic analyzer Setup and Trigger window, select the Format tab. b Under the Format tab, select Pod Assignment. c In the Pod Assignment window, use the mouse to drag the pods to the Analyzer 1 column. d Select Close to close the pod assignment window.
Chapter 5: Troubleshooting e Under the Format tab, select the field showing the channel assignments for one of the pods being tested, then select “****************” to active all channels. f Select OK to close the channel assignment window. g Repeat e and f for the remaining pods to be tested. 7 Configure the logic analyzer thresholds a In the logic analyzer Setup and Trigger window, select the Format tab. b Under the Format tab, select the threshold field under either pod.
Chapter 5: Troubleshooting d In the Pod threshold window, select User Defined, then select the threshold voltage field. Enter 1.00V. e Select Close to close the pod threshold window. f Under the Format tab, select the Clk Thresh... field. The clock threshold window will appear. g Select the threshold field associated with J-clock. The J threshold window will appear. h In the J threshold window, select Differential.
Chapter 5: Troubleshooting 8 On the logic analyzer, select Run. The listing should look similar to the figure below. Scroll down at least 256 states to verify the data. The lower two bytes (four digits) of Label1 show two incrementing binary counters. The upper two bytes of Label1 show two decrementing binary counters. If the listing does not look similar the figure, then there is a possible problem with the cable or high density adapter.
Chapter 5: Troubleshooting b On the logic analyzer, select Run. Note the lower two bytes now displays two decrementing counters, the upper two bytes displays two incrementing counters. If the error in the test data remains the same two bytes as the previous run (that is, the error follows the cable) then the cable is suspect. If the error is now in the opposite two bytes (that is, the error follows the E5378A probe adapter) the probe adapter is suspect. Return to the troubleshooting flowchart.
Chapter 5: Troubleshooting To test the cables using an Agilent E5379A Differential Probe This test allows you to functionally verify the logic analyzer cable and an Agilent E5379A probe. Equipment Required Equipment Critical Specification Recommended Part Stimulus Board No Substitute 16760-60001 1 Connect the logic analyzer to the stimulus board. a Connect an Agilent E5379A 100-pin differential probe to the logic analyzer cable to be tested.
Chapter 5: Troubleshooting 2 Set up the stimulus board a Configure the oscillator select switch S1 according to the following settings: • S1 Off • S2 Off • S3 Off • Int b Configure the data mode switch S4 according to the following settings: • Even • Count c Press the Resynch VCO button, then the Counter RST (Counter Reset) button. 3 Set up the logic analyzer a Open the Session Manager window and select “Start Session.
Chapter 5: Troubleshooting c Select the clock edge field for J-clock, then select Rising Edge. 5 Configure the Trigger settings a In the logic analyzer Setup and Trigger window, select the Trigger tab. b Under the Trigger tab, select the Settings tab. c Select the Acquisition Depth field, then select 8K. d Select the Trigger Position field, then select Start. e Select the Count field, then select Off.
Chapter 5: Troubleshooting 6 Configure the Format tab a In the logic analyzer Setup and Trigger window, select the Format tab. b Under the Format tab, select Pod Assignment. c In the Pod Assignment window, use the mouse to drag the pod under test to the Analyzer 1 column. d Select Close to close the pod assignment window. e Under the Format tab, select the field showing the channel assignment for the pod under test, then select “****************” to activate all channels.
Chapter 5: Troubleshooting 7 Configure the logic analyzer thresholds a Under the Format tab, select the CLK Thresh... field. The Clock threshold window will appear. b Select the threshold field associated with J-clock. The J threshold window will appear. c In the J threshold window, select Differential. d Select Close to close the J threshold window, then select Close to close the Clock threshold window. 8 On the logic analyzer, select Run. The listing should look similar to the figure below.
Chapter 5: Troubleshooting Scroll down at least 256 states to verify the data. Label1 shows two decrementing binary counters. If the listing does not look similar to the figure, then there is a possible problem with the cable or high density probe adapter. Cause for cable test failures include: • open channel • channel shorted to a neighboring channel • channel shorted to either ground or a supply voltage If the test data is not correct, then perform the following step to isolate the failure.
6 Replacing Assemblies This chapter contains the instructions for removing and replacing the logic analyzer module, the circuit board of the module, and the probe cables of the module as well as the instructions for returning assemblies.
Chapter 6: Replacing Assemblies CAUTION: Turn off the instrument before installing, removing, or replacing a module in the instrument. Tools Required • A T10 TORX screwdriver, to remove screws connecting the probe cables and screws connecting the back panel. To remove the module CAUTION: Electrostatic discharge can damage electronic components. Use grounded wriststraps and mats when performing any service to this module. 1 Remove power from the instrument. a Exit all logic analysis sessions.
Chapter 6: Replacing Assemblies 5 Push all other cards into the card cage, but not completely in. This is to get them out of the way for removing and replacing the module. 6 If the module consist of a single card, replace the faulty card. If the module consists of multiple cards, remove the cables from J9 and J10 of all cards. Remove the 2x10 cables from J4, J5, J7, and J8 from the master card. Remove the faulty card from the module.
Chapter 6: Replacing Assemblies To remove the logic analyzer cable 1 Remove power from the instrument a Exit all logic analysis session. In the session manager, select Shutdown. b At the query, select Power Down. c When the “OK to power down” message appears, turn the instrument off. d Disconnect the power cord. 2 Remove the logic analyzer cable clamp. a Remove two screws that secure the top logic analyzer cable clamp to the outside rear panel.
Chapter 6: Replacing Assemblies To install the logic analyzer cable 1 Connect the logic analyzer cable to the logic analyzer circuit board. a Insert the logic analyzer cable to the logic analyzer circuit board. b Align the logic analyzer cable end connector with the circuit board cable connector (J1 or J2) and gently apply pressure to seat the logic analyzer cable onto the circuit board connector. c Insert the top and bottom logic analyzer cable clamps into the rear panel.
Chapter 6: Replacing Assemblies b Install the two shorter screws (H4) through the rear of both cable clamps into the rear panel. Do not tighten the screws yet. c Tighten the short rear panel cable clamp screws (H4) to 5 in/lb. Then tighten the longer cable clamp screws (H5) to 5 in/lb. CAUTION: If you over tighten the screws, the threaded inserts on the rear panel, the threaded inserts on the circuit board, or the cable clamp itself might break.
Chapter 6: Replacing Assemblies To replace the circuit board 1 Remove both logic analyzer cables using the “To remove the logic analyzer cable” procedure on page 130. 2 Remove the four screws attaching the ground spring and back panel to the circuit board, then remove the back panel and the ground spring. 3 Replace the faulty circuit board with a new circuit board. On the faulty board, make sure the 20-pin ribbon cable is connected between J3 and J6.
Chapter 6: Replacing Assemblies To replace the module 1 If the module consists of one card, go to step 2. If the module consists of more than one card, connect the cables together in a master/expander configuration. Follow the procedure “To configure a multi-card module” on page 20. 2 Slide the cards above the slots for the module about halfway out of the mainframe. 3 With the probe cables facing away from the instrument, slide the module approximately halfway into the mainframe.
Chapter 6: Replacing Assemblies 5 Position all cards and filler panels so that the endplates overlap. 6 Seat the cards and tighten the thumbscrews. Starting with the bottom card, firmly seat the cards into the backplane connector of the mainframe. Keep applying pressure to the center of the card endplate while tightening the thumbscrews finger-tight. Repeat this for all cards and filler panels starting at the bottom and moving to the top.
Chapter 6: Replacing Assemblies To return assemblies Before shipping the module to Agilent Technologies, contact your nearest Agilent Technologies Sales Office for additional details. Information on contacting Agilent can be found at http://www.agilent.com. 1 Write the following information on a tag and attach it to the module. • Name and address of owner • Model number • Serial number • Description of service required or failure indications 2 Remove accessories from the module.
7 Replaceable Parts This chapter contains information for identifying and ordering replaceable parts for your module.
Chapter 7: Replaceable Parts Replaceable Parts Ordering Parts listed To order a part on the list of replaceable parts, quote the Agilent Technologies part number, indicate the quantity desired, and address the order to the nearest Agilent Technologies Sales Office. Parts not listed To order a part not on the list of replaceable parts, include the model number and serial number of the module, a description of the part (including its function), and the number of parts required.
Chapter 7: Replaceable Parts Agilent Technologies Sales Office for information. See Also “To return assemblies” on page 136. Replaceable Parts List The replaceable parts list is organized by reference designation and shows exchange assemblies, electrical assemblies, then other parts.
Chapter 7: Replaceable Parts Replaceable Parts Ref. Des. Agilent Part Number QTY Description Exchange Assemblies 16760-69516 Replacement Assemblies A1 16760-66516 1 Acquisition Board Assembly H1 H2 H3 H4 H5 16500-22401 16500-29101 0510-0684 0515-0372 0515-0375 2 1 2 4 4 H6 0515-0430 3 Panel Screw Ground Spring Retaining Ring M3.0x0.5 8mm T10 (Cable Clamp to Rear Panel) M3.0x0.5 16mm T10 (Cable Clamp to Acquisition Board) MSPH M3.0x0.
Chapter 7: Replaceable Parts Exploded View Exploded view of the 16760A logic analyzer 141
Chapter 7: Replaceable Parts E5382A Accessories The following figure shows the accessories supplied with the E5382A Single-ended Flying Lead Probe Set. Accessories supplied The following table shows the part numbers for ordering replacement parts and additional accessories.
8 Theory of Operation This chapter presents the theory of operation for the logic analyzer module and describes the self-tests.
Chapter 8: Theory of Operation The information in this chapter is to help you understand how the module operates and what the self-tests are testing. This information is not intended for component-level repair. Block-Level Theory The block-level theory of operation is divided into two parts: theory for the logic analyzer used as a single-card module or as a master card in a multi-card module, and theory for the logic analyzer used as an expander card in a multi-card module.
Chapter 8: Theory of Operation connector. The mate to this Samtec connector must be designed into and installed in the system under test. Analysis of single-ended or differential signals is performed depending on whether the single-ended or differential probe adapter is used. A Mictor-compatible probe adapter is also available. Like the Samtec probe adapter, the Mictor probe adapter is used for single-ended signal analysis through a Mictor connector designed in and installed into a system under test.
Chapter 8: Theory of Operation state clock modes and configuration are also done by the comparators. A digitalto-analog convertor (DAC) provides the module threshold voltage for singleended operation. The voltage at the DAC outputs are buffered to prove sufficient line drive. An analog switch is used to channel either the module threshold voltage from the DAC or the threshold voltage input from the system under test to the comparators. High Speed Gate Array.
Chapter 8: Theory of Operation CPU Interface. The CPU interface is a programmable logic device that converts the bus signals generated by the microprocessor on the mainframe CPU card into control signals for the logic analyzer module. All functions of the state and timing module can be controlled from the backplane of the mainframe system including storage qualification, sequencing, assigning clock edges, RUN and STOP, and thresholds.
Chapter 8: Theory of Operation Connectors J9, J10, J500, and J501 form and acquisition IC pattern resource bus. In addition to the master board, identification and operational configuration of the expander boards are done through the CPU interface.
Index A accessories, 10 acquisition, 106 IC, 146 memory, 146 ADC test, 110 assemblies exchange, 138 return, 136 B block-level theory, 144 C cable install, 131 remove, 130 test E5378A cable, 113 test E5379A cable, 121 calibrating see also testing performance calibration, 99 strategy, 100 characteristics, 12 environmental, 12 circuit board replace, 133 clean module, 29 cleaning the instrument, 151 comparators, 145 comparators calibration test, 111 comparators programming test, 110 comparators V offset test,
Index system backplane clock, 109 system clocks, 108 testing performance, 31 equipment, 13, 33 interval, 32 multi-card module, 32 test record, 96 theory of operation, 143 tools required, 128 troubleshooting, 101 S self-test, 105 description, 106 specifications, 11 storage, 16 system backplane clock, 109 operating, 10, 102 test, 112 turn on, 28 T test ADC, 110 analyzer chip memory bus, 108 analyzer memory bus SU/H measure, 109 chip registers, 108 comparators calibration, 111 comparators programming, 110 co
Safety Notices This apparatus has been designed and tested in accordance with IEC Publication 1010, Safety Requirements for Measuring Apparatus, and has been supplied in a safe condition. This is a Safety Class I instrument (provided with terminal for protective earthing). Before applying power, verify that the correct safety precautions are taken (see the following warnings). In addition, note the external markings on the instrument that are described under "Safety Symbols.
Notices © Agilent Technologies, Inc. 20012004 No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Agilent Technologies, Inc. as governed by United States and international copyright laws.
