Specifications

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Chapter 5: Troubleshooting
by each chip in the module.
Inter-module Flag Bits Test. The purpose of this test is to verify that the 4
Inter-module Flag Bit Output lines can be driven out from the master chip in the
module and received by each chip in the module.
Global and Local Arm Lines Test. The purpose of this test is to verify that
each Analysis chip on the master board can receive the Local Arm signal, and the
Global Arm signal can be driven by the bottom and top chips on the master board
and received by all chips in the module (master and slave). Note that the middle
analysis chip cannot drive the Global Arm signal (left unconnected).
Timing Zoom Memory BIST Test. This test verifies that the timing zoom
SRAM embedded in the analysis chips is functional.
Timing Zoom Memory Addr/Data Test. This test verifies connectivity of
components within the analysis chip. It verifies that the address, data, and clock
lines of the timing zoom circuitry is correct.