Service Guide Publication number 16910-97000 April 2004 For Safety and Regulatory information, see the pages at the end of the book. © Copyright Agilent Technologies 2001-2004 All Rights Reserved.
Chapter : The Agilent 16910/11A Logic Analyzers—At a Glance The Agilent Technologies 16910A and 16911A are logic analyzer modules for the Agilent Technologies 16900-series logic analysis system. The 16910/11A offers high performance measurement capability.
Chapter : The 16910A Logic Analyzer The 16911A Logic Analyzer 3
In This Book This book is the service guide for the 16910A and 16911A logic analyzer modules. This service guide has eight chapters. Chapter 1, “General Information,” beginning on page 9 contains information about the module and includes accessories for the module, specifications and characteristics of the module, and a list of the equipment required for servicing the module. Chapter 2, “Preparing for Use,” beginning on page 15 tells how to inspect and prepare the module for use.
Contents 1 General Information Accessories 10 Mainframe and Operating System 10 Specifications 11 Environmental Characteristics 12 Recommended Test Equipment 13 2 Preparing for Use Power Requirements 16 Operating Environment 16 Storage 16 To inspect the module 16 To configure and install the module To test the module 17 To clean the module 17 17 3 Testing Logic Analyzer Performance To Assemble the SMA/Flying Lead Test Connectors 22 To Test the Minimum Master to Master Clock Time and Minimum Eye Width
Contents Test Pod 1 in 250 Mb/s Mode 47 Determine PASS/FAIL (1 of 2 tests) 47 Close the Eye Finder and Analyzer Setup Windows 47 Configure the markers 47 Determine PASS/FAIL (2 of 2 tests) 49 Test the complement of the bits (250 Mb/s mode) 50 Test Pod 2 in 250 Mb/s Mode 52 Test the complement of the bits (Pod 2, 250 Mb/s mode) Test the Remaining Pods in 250 Mb/s Mode Test Pod 1 in 500 Mb/s Mode 53 54 54 Determine and set Eye Finder Position (500 Mb/s mode) 55 Test the complement of the bits (Pod
Contents 6 Replacing Assemblies Tools Required 84 To remove the module 84 To remove the logic analyzer cable 85 To install the logic analyzer cable 86 To replace the circuit board 87 To return assemblies 88 7 Replaceable Parts Ordering Replaceable Parts 90 Replaceable Parts List 91 16910A Exploded View 94 16911A Exploded View 95 8 Theory of Operation Block-Level Theory 98 Index 7
Contents 8
1 General Information This chapter lists the accessories, some of the specifications and characteristics, and the recommended test equipment.
Chapter 1: General Information Accessories One or more of the following accessories, sold separately, are required to operate the 16910/11A logic analyzers.
Chapter 1: General Information Specifications The specifications are the performance standards against which the product is tested. tWidth (Data Eye) Individual Data Channel vHeight Sampling Position (Eye Finder Blue Bar) vThreshold 0V 16753b01.vsd Specifications 250 Mb/s mode 500 Mb/s mode Minimum master to master clock time 4 ns 2 ns 500 Mb/s mode is available only when Option 500 is installed. tWidth (minimum) 1.5 ns 1.5 ns Specified at probe tip.
Chapter 1: General Information Environmental Characteristics Probes Maximum Input Voltage ± 40 V, CAT I, CAT I = Category I, secondary power line isolated circuits. Operating Environment Temperature Humidity Altitude Vibration 0 to 40 °C (+32 °F to 104 °F) when operating in a 16900A or 16902A mainframe. 0 to 50 °C (+32 °F to 122 °F) when operating in a 16903A mainframe. Up to 80% relative humidity at 40 °C (+104 °F). Reliability is enhanced when operating within the range 20% to 80% non-condensing.
Chapter 1: General Information Recommended Test Equipment Recommended Test Equipment Equipment Critical Specifications Recommended Agilent Model/Part Use† Single-ended Flying Lead Probe Set (Qty 2) no substitute E5383A P, T Ground Leads (Qty 5) no substitute pkg of 5 (Included with E5383A Probe Set) T Pulse Generator 260 MHz,1 ns pulse width, two channels, ≤ 150 ps rise time 8133A Option 003 P, T 150 ps Transition Time Converter (Qty 4) Required if pulse generator’s rise time is less than
Chapter 1: General Information 14
2 Preparing for Use This chapter gives you instructions for preparing the logic analyzer module for use.
Chapter 2: Preparing for Use Power Requirements All power supplies required for operating the logic analyzer are supplied through the backplane connector in the mainframe. Operating Environment The operating environment is listed on page 12. Note the non-condensing humidity limitation. Condensation within the instrument can cause poor operation or malfunction. Provide protection against internal condensation.
Chapter 2: Preparing for Use mechanical defects. If you find any defects, contact your nearest Agilent Technologies Sales Office. Arrangements for repair or replacement are made, at Agilent Technologies' option, without waiting for a claim settlement. To configure and install the module Instructions for configuring and installing the module into the mainframe can be found in the installation guide for the mainframe.
Chapter 2: Preparing for Use 18
3 Testing Logic Analyzer Performance This chapter tells you how to test the performance of the 16910A or 16911A logic analyzer against the specifications listed on page 11.
Chapter 3: Testing Logic Analyzer Performance To ensure the 16910A or 16911A logic analyzer (also referred to as the module or the card) is operating as specified, software tests (self-tests) and a manual performance test are done. The logic analyzer is considered performance-verified if all of the software tests and the manual performance test have passed. The procedures in this chapter indicate what constitutes a “Pass” status for each of the tests.
Chapter 3: Testing Logic Analyzer Performance Test Equipment Each procedure lists the recommended test equipment. You can use equipment that satisfies the specifications given. However, the procedures are based on using the recommended model or part number. Instrument Warm-Up Before testing the performance of the module, warm-up the logic analyzer and the test equipment for 30 minutes.
Chapter 3: Testing Logic Analyzer Performance To Assemble the SMA/Flying Lead Test Connectors To Assemble the SMA/Flying Lead Test Connectors The SMA/Flying Lead test connectors provide a high-bandwidth connection between the logic analyzer and the test equipment. The following procedure explains how to fabricate the required test connectors. Materials Required Material Critical Specification SMA Board Mount Connector (Qty 6) Recommended Model/Part Johnson 142-0701-801 (see www.johnsoncomponents.
Chapter 3: Testing Logic Analyzer Performance To Assemble the SMA/Flying Lead Test Connectors b Trim about 1.5 mm from the pin strip inner leads and straighten them so that they touch the outer leads. c Trim about 2.5 mm from the outer leads. solder d Using a very small amount of solder, tack each inner lead to each outer lead at the point where they are touching.
Chapter 3: Testing Logic Analyzer Performance To Assemble the SMA/Flying Lead Test Connectors 2 Solder the pin strip to the SMA board mount connector: a Solder the leads on the left side of the pin strip to the center conductor of the SMA connector as shown in the diagram below. b Solder the leads on the right side of the pin strip to the inside of the SMA connector’s frame as shown in the diagram below. Use a small amount of solder.
Chapter 3: Testing Logic Analyzer Performance To Assemble the SMA/Flying Lead Test Connectors c Rotate the assembly 180 degrees and solder the two SMA board mount connector frames together. 4 Check your work: a Ensure that the following four points have continuity between them: The two pins on the left side of the pin strip, and the center conductors of each SMA connector. b Ensure that there is continuity between each of the two pins on the right side of the pin strip, and the SMA connector frames.
Chapter 3: Testing Logic Analyzer Performance To Assemble the SMA/Flying Lead Test Connectors c The finished test connector is shown in the pictures below.
Chapter 3: Testing Logic Analyzer Performance To Test the Minimum Master to Master Clock Time and Minimum Eye Width To Test the Minimum Master to Master Clock Time and Minimum Eye Width The specifications for the 16910/11A logic analyzer define a minimum master to master clock time and a minimum data eye width at which data can be acquired. This test verifies that the logic analyzer meets these specifications. Eye Finder is used to adjust the sampling position on every tested channel.
Chapter 3: Testing Logic Analyzer Performance Equipment Required Equipment Required The following equipment is required for the performance test procedure. Equipment Required Equipment Critical Specification Pulse Generator ≥ 260 MHz, two channels, differential Agilent or HP 8133A option 003 outputs, 150-180 ps rise/fall time (if faster, use transition time converters) 150 ps Transition Time Converter Required if pulse generator’s rise time is (Qty 3) less than 150 ps.
Chapter 3: Testing Logic Analyzer Performance Prepare the Logic Analysis System for Testing Prepare the Logic Analysis System for Testing 1 Record the 16910A or 16911A logic analyzer’s model and serial number in the Performance Test Record (see page 60). Record your work order number (if applicable) and today’s date. 2 Record the test equipment information in the “Test Equipment Used” section of the Performance Test Record. 3 Turn on the logic analysis system.
Chapter 3: Testing Logic Analyzer Performance Prepare the Logic Analysis System for Testing Perform System Self-Tests 5 Do a self-test on the logic analysis system. a When the logic analysis system has finished booting, the Waveform window appears. Select Help→Self-Test... from the main menu. The Analysis System Self Tests window will appear. b In the Select Suite(s) list, select . This will cause to be selected in the Select Test(s) list. c Select Start.
Chapter 3: Testing Logic Analyzer Performance Set Up the Test Equipment Set Up the Test Equipment 1 Turn on the required test equipment. Let all of the test equipment and the logic analyzer warm up for 30 minutes before beginning any test. 2 Set up the pulse generator according to the following table. a Set the frequency of the pulse generator. In this test procedure, the logic analyzer uses both edges of the clock to acquire data.
Chapter 3: Testing Logic Analyzer Performance Set Up the Test Equipment 3 Set up the oscilloscope. a Set up the oscilloscope according to the following tables. Oscilloscope Setup Setup: Channel 1 Setup: Ch. 1 Probe Setup: Channel 2 Setup: Ch. 2 Probe On Attenuation: 1.00:1 On Attenuation: 1.
Chapter 3: Testing Logic Analyzer Performance Connect the Test Equipment Connect the Test Equipment Connect the 16910/11A Logic Analyzer Pod to the 8133A Pulse Generator 1 Connect a Transition Time Converter (if required—see page 28) to each of the four outputs of the 8133A pulse generator except Channel 1 OUTPUT.
Chapter 3: Testing Logic Analyzer Performance Connect the Test Equipment 5 Connect the E5383A Flying Lead Probe Set’s CLK lead to the pin strip of the SMA/Flying Lead connector at the 8133A pulse generator’s Channel 1 OUTPUT.
Chapter 3: Testing Logic Analyzer Performance Connect the Test Equipment 7 Connect the E5383A Flying Lead Probe Set’s bits 6 and 14 to the SMA/ Flying Lead test connector’s pin strip connector at the 8133A pulse generator’s Channel 2 OUTPUT. Connect the 8133A Pulse Generator Output to the 54845A Oscilloscope 8 Attach Male BNC to Female SMA adapters to Channels 1 and 2 on the 54845A oscilloscope. 9 Attach one end of an SMA cable to the Male BNC to Female SMA adapter on Channel 1 of the oscilloscope.
Chapter 3: Testing Logic Analyzer Performance Connect the Test Equipment Verify and adjust 8133A pulse generator DC offset 1 On the 54845A oscilloscope, select Measure from the menu bar at the top of the display. 2 Select Markers... 3 In the Markers Setup window set marker “Ay” to 0.7 V, and set marker “By” to 1.3 V. 4 Observe the waveforms on the oscilloscope display.
Chapter 3: Testing Logic Analyzer Performance Connect the Test Equipment Deskew the oscilloscope This procedure neutralizes any skew in the oscilloscope’s waveform display. 1 On the 54845A oscilloscope, change the Horizontal scale to 200 ps/div. You can do this using the large knob in the Horizontal setup section of the front panel. 2 Select Setup from the menu bar at the top of the display. 3 Select Channel 1. 4 Select Probes.
Chapter 3: Testing Logic Analyzer Performance Connect the Test Equipment was set to 1 volt in the oscilloscope setup described on page 32. 6 Select Close in the Probe Setup window. 7 Select Close in the Channel Setup window.
Chapter 3: Testing Logic Analyzer Performance Connect the Test Equipment Set the 8133A pulse width 1 On the 8133A pulse generator, set the Channel 2 pulse width to 1.5 ns. 2 Observe the 54845A oscilloscope display. Change the Channel 2 pulse width of the 8133A pulse generator so that the pulse width measured at 1 volt on the oscilloscope is equal to 1.5 ns minus the measurement uncertainty and display resolution of the oscilloscope, further reduced by 35 ps for test margin.
Chapter 3: Testing Logic Analyzer Performance Configure the Logic Analysis System Configure the Logic Analysis System 1 Exit the logic analysis application (from the main menu, choose File→Exit) and then restart the application. This puts the logic analysis system into its initial state. 2 Disable all logic analyzers other than the analyzer under test. a Select the Overview tab at the bottom of the main window. b Click on each unused logic analyzer and select disable.
Chapter 3: Testing Logic Analyzer Performance Configure the Logic Analysis System The Threshold Settings window will appear. Click here c Set the threshold value for Pod 1 of the 16910/11A logic analyzer to 1 V and select OK. d The activity indicators will now show activity on the channels that are connected to the pulse generator. e Un-assign all channels. Hint: you can do this quickly by clicking on the left-most check mark and dragging to the right across all of the other check marks.
Chapter 3: Testing Logic Analyzer Performance Configure the Logic Analysis System mainframe you can touch the touchscreen and drag across with your finger. f Click (or touch) to select channels 2, 6, 10 and 14 as shown. g Drag the scroll bar all the way to the left and ensure that the activity indicator shows activity on clock 1. 4 Set the sampling mode. a Select the Sampling tab of the Analyzer Setup window. b Select State Mode. c Set the Trigger Position to 100% Poststore.
Chapter 3: Testing Logic Analyzer Performance Configure the Logic Analysis System f Ensure that the sampling speed is set to 250 MHz in the Sampling Options box. NOTE: If option 500 is not installed on the 16910/11A module, then 250 MHz will be the only speed available. g Ensure that the Clock Mode is set to Master. h Set the clock mode to Both Edges.
Chapter 3: Testing Logic Analyzer Performance Configure the Logic Analysis System Adjust the sample positions using Eye Finder 1 Select the Sample Positions button. The Eye Finder window will appear. 2 In the “Buses/Signals” section of the Eye Finder window, ensure that the check box next to “My Bus 1” is checked. 3 Select the plus sign to expand bus “My Bus 1”. Align the blue bars vertically The first time you run Eye Finder, the blue bars will already be vertically aligned (as shown above).
Chapter 3: Testing Logic Analyzer Performance Configure the Logic Analysis System Run Eye Finder 6 Select the Run button in the Eye Finder window. 7 Ensure that an eye appears for each bit near the recommended starting position. Depending on your test setup, the eye position may vary. Any skew between channel 1 and channel 2 of your pulse generator will cause the eye position to shift to the left or right in the Eye Finder display. A shift of up to 0.5 ns should be considered normal.
Chapter 3: Testing Logic Analyzer Performance Configure the Logic Analysis System To re-align a stray channel If the blue bar for a particular bit does not appear in its eye near the recommended starting position, then do the following steps to realign the sampling position of the stray channel. In the following example, the sampling position of one channel (My Bus 1 [2]) must be realigned with the sampling position of the other channels.
Chapter 3: Testing Logic Analyzer Performance Test Pod 1 in 250 Mb/s Mode Test Pod 1 in 250 Mb/s Mode The steps that follow include pass/fail criteria. Determine PASS/FAIL (1 of 2 tests) 1 PASS/FAIL: If an eye exists near 300 ps for every bit, and Eye Finder places a blue bar in the narrow eye for each bit, then the logic analyzer passes this portion of the test. Record the result in the “Test 1 of 2: Eye Finder locates an eye for each bit” section of the Performance Test Record (page 60).
Chapter 3: Testing Logic Analyzer Performance Test Pod 1 in 250 Mb/s Mode 3 Data will appear in the Listing Window upon completion of the run. 4 From the Main Menu choose Markers→New. a You can accept the default name for the new marker. b Change the Position field to Value. c Select the Occurs... button and create the marker setup shown below. Click here to add event Click here to select “Or” 5 In the Value window, select the Properties... button.
Chapter 3: Testing Logic Analyzer Performance Test Pod 1 in 250 Mb/s Mode 9 Select OK to close the New Marker window. Determine PASS/FAIL (2 of 2 tests) Pass/Fail Point: The Listing window is set up to search for the appropriate number of A's and 5's in the acquisition. If the logic analyzer does not detect the correct number of A’s and 5’s, an error window will appear. 1 Select the Run Repetitive icon . Let the logic analyzer run for about one minute.
Chapter 3: Testing Logic Analyzer Performance Test Pod 1 in 250 Mb/s Mode NOTE: As a point of curiosity, you may want to determine the absolute minimum pulse width and/or absolute maximum frequency at which data can be acquired. The “Performance Test Record” on page 60 does not include places for recording these values because the Performance Verification procedure only verifies that the logic analyzer meets specifications.
Chapter 3: Testing Logic Analyzer Performance Test Pod 1 in 250 Mb/s Mode markers. See page 39 for details. 6 Adjust the sampling positions using Eye Finder. See page 44. 7 Determine pass or fail (1 of 2 tests). See page 47. 8 Switch to the Listing window by selecting the Listing tab at the bottom of the main logic analyzer window. 9 Select the Run Repetitive icon . 10 Determine pass or fail (2 of 2 tests). See page 49.
Chapter 3: Testing Logic Analyzer Performance Test Pod 2 in 250 Mb/s Mode Test Pod 2 in 250 Mb/s Mode 1 Disconnect the E5383A Flying Lead Probe Set from Pod 1 and connect it to Pod 2 of the logic analyzer. Do not remove the flying leads that are connected to CLK and the data channels. 2 On the 8133A pulse generator, in the PULSE setup for CHANNEL 2, press the COMP button to return the outputs to normal. 3 Note that the signal on the oscilloscope has moved.
Chapter 3: Testing Logic Analyzer Performance Test Pod 2 in 250 Mb/s Mode 13 Adjust the sampling positions using Eye Finder. Be sure to expand “My Bus 1” and use the recommended starting position noted on page 44. Realign any stray channels if necessary. See page 46. 14 Determine pass or fail (1 of 2 tests). See page 47. 15 Select OK to close the “Analyzer Setup” window. 16 Switch to the Listing window by selecting the Listing tab at the bottom of the main logic analyzer window.
Chapter 3: Testing Logic Analyzer Performance Test the Remaining Pods in 250 Mb/s Mode Test the Remaining Pods in 250 Mb/s Mode 1 Perform the normal and complement tests for each additional pod on the logic analyzer, changing the connection to the pod, channel assignments, thresholds, etc. as appropriate. Test using clock Clk3 for Pod 3, clock Clk4 for Pod 4, etc. Upon completion, the logic analyzer is completely tested in the 250 Mb/s mode. The 16910A has six pods; the 16911A has four pods.
Chapter 3: Testing Logic Analyzer Performance Test Pod 1 in 500 Mb/s Mode 5 Assign bits 2, 6, 10, and 14 of Pod 1. 6 Ensure that the Pod 1 threshold is set to 1 volt. See page 41. Determine and set Eye Finder Position (500 Mb/s mode) 7 On the 8133A pulse generator, in the PULSE setup for CHANNEL 2, press the COMP button to return the outputs to normal. 8 Change the oscilloscope’s horizontal position to 725 ps (or as required) to center the measured pulse on the oscilloscope display.
Chapter 3: Testing Logic Analyzer Performance Test Pod 1 in 500 Mb/s Mode See page 46. 18 Now set the pulse generator to the new test frequency. The logic analyzer will be tested using a double-edge clock. The test frequency is half the test clock rate because data is acquired on both the rising edge and the falling edge of the clock. Set the frequency to 250 MHz plus the frequency uncertainty of the pulse generator, plus a test margin of 1%.
Chapter 3: Testing Logic Analyzer Performance Test Pod 2 in 500 Mb/s Mode Yes to erase the data and continue. 25 Perform the procedure “Determine PASS/FAIL (1 of 2 tests)” on page 47. 26 Select the Run Repetitive icon . 27 Perform the procedure “Determine PASS/FAIL (2 of 2 tests)” on page 49. Test the complement of the bits (Pod 1, 500 Mb/s mode) Now test the logic analyzer using complement data. 1 On the 8133A pulse generator, in the PULSE setup for CHANNEL 2, select COMP.
Chapter 3: Testing Logic Analyzer Performance Test Pod 2 in 500 Mb/s Mode SMA/Flying Lead test connector’s pin strip connector at the 8133A pulse generator’s Channel 2 OUTPUT. 4 Connect the Pod 2 E5383A Flying Lead Probe Set’s bits 2 and 10 to the SMA/Flying Lead test connector’s pin strip connector at the 8133A pulse generator’s Channel 2 OUTPUT. 5 On the 8133A pulse generator, in the PULSE setup for CHANNEL 2, press the COMP button to return the outputs to normal.
Chapter 3: Testing Logic Analyzer Performance Test Pods 3 and 4 in 500 Mb/s Mode (16910A only) Test Pods 3 and 4 in 500 Mb/s Mode (16910A only) 1 Perform the normal and complement tests for each additional pod on the logic analyzer, changing the connection to the pod, channel assignments, thresholds, etc. as appropriate. You must use clock Clk1 on Pod 1 for all tests in the 500 Mb/s mode because the other clocks are not available in this mode. Upon completion, the logic analyzer is completely tested.
Chapter 3: Testing Logic Analyzer Performance Performance Test Record Performance Test Record LOGIC ANALYZER MODEL NO. (circle one): 16910A 16911A Logic Analyzer Serial No. Work Order No. Date: Recommended Test Interval - 2 Years Recommended next testing: TEST EQUIPMENT USED Pulse Generator Model No. Oscilloscope Model No. Pulse Generator Serial No. Oscilloscope Serial No.
4 Calibrating This chapter gives you instructions for calibrating the logic analyzer.
Chapter 4: Calibrating Calibration Strategy The 16910/11A logic analyzer does not require an operational accuracy calibration. To test the module against the module specifications, refer to the “Testing Logic Analyzer Performance” chapter on page 19.
5 Troubleshooting This chapter helps you troubleshoot the module to find defective assemblies.
Chapter 5: Troubleshooting The troubleshooting consists of flowcharts, self-test instructions, and a cable test. If you suspect a problem, start at the top of the first flowchart. During the troubleshooting instructions, the flowcharts will direct you to perform the selftests or the cable test. The service strategy for this instrument is the replacement of defective assemblies. This module can be returned to Agilent Technologies for all service work, including troubleshooting.
Chapter 5: Troubleshooting Troubleshooting Flowchart 1 65
Chapter 5: Troubleshooting Troubleshooting Flowchart 2 66
Chapter 5: Troubleshooting To run the self tests 1 See “Perform System Self-Tests” on page 30. Self-Test Descriptions The self-tests for the logic analyzer identify the correct operation of major functional areas in the module. Interface FPGA Register Test. The purpose of this test is to verify that the backplane interface can communicate with the backplane FPGA. This FPGA must be working before any of the other circuits on the board will work.
Chapter 5: Troubleshooting modes of unloading data from the acquisition RAM devices. These modes are setup by writing to registers in the Memory Controller FPGAs. These FPGAs sequence the data and perform data decoding based on the mode. DMA Test. The purpose of this test is to check the various modes of unloading data from the acquisition RAM memories using DMA backplane transfers.
Chapter 5: Troubleshooting by each chip in the module. Inter-module Flag Bits Test. The purpose of this test is to verify that the 4 Inter-module Flag Bit Output lines can be driven out from the master chip in the module and received by each chip in the module. Global and Local Arm Lines Test.
Chapter 5: Troubleshooting To exit the test system 1 Simply close the self-test window. No additional actions are required.
Chapter 5: Troubleshooting To Assemble the 2 x 9 Test Connectors To Assemble the 2 x 9 Test Connectors The 2 x 9 test connectors are used to connect all 16 channels and the clock of the logic analyzer to the pulse generator so you can test the flying lead probe and cables. (See “To test the cables” on page 73.) Materials Required Material Critical Specification Recommended Model/Part Pin Strip Header (Qty 1, which will be separated) .100" x .
Chapter 5: Troubleshooting To Assemble the 2 x 9 Test Connectors pins. e Repeat for the second 2 x 9 pin strip. 2 Attach the SMA connector: a Solder the center pin of the SMA connector to the center pin of one row on the pin strip. b Solder the ground tab of the SMA connector to the pins of the other row on the pin strip. c Repeat for the second 2 x 9 pin strip. 3 Check your work and de-flux the assembies if desired.
Chapter 5: Troubleshooting To test the cables To test the cables This test allows you to functionally verify the logic analyzer cable and the flying lead probe of any of the logic analyzer pods. Only one probe and cable can be tested at a time. Repeat this test for each probe and cable to be tested. Two Flying Lead Probes are required if you need to test pods other than Pod 1 because the clock from Pod 1 will be used to acquire data.
Chapter 5: Troubleshooting To test the cables Connect the test equipment 1 Using two 2 x 9 test connectors, connect the logic analyzer to the pulse generator channel outputs. a Connect the even-numbered channels to the pulse generator Channel 2 OUTPUT. b Connect the odd-numbered channels the pulse generator Channel 2 OUTPUT. 2 Connect Clk1 to the pulse generator Channel 2 OUTPUT. 3 Enable the pulse generator Channel 1 and Channel 2 outputs (LEDs off).
Chapter 5: Troubleshooting To test the cables 3 Set up the bus and signals to test Pod 1. a From the Logic Analysis System main menu, select Setup→My 1691xA→Bus/Signal.... b In the Analyzer Setup window, ensure that the Threshold button for Pod 1 is set to TTL (1.50 V). Threshold c Verify that the activity indicators (the red arrows) show activity on all 16 channels that are connected to the pulse generator. d Assign all channels.
Chapter 5: Troubleshooting To test the cables indicator shows activity on clock 1. 4 Set the sampling mode. a Select the Sampling tab of the Analyzer Setup window. b Select State Mode. c Set the Trigger Position to 100% Poststore. d Set the Acquisition Depth to 128K. e Clear the Timing Zoom check box to turn Timing Zoom off. f Ensure that the sampling speed is set to 250 MHz in the Sampling Options box.
Chapter 5: Troubleshooting To test the cables NOTE: If option 500 is not installed on the 16910/11A module, then 250 MHz will be the only speed available. g Ensure that the Clock Mode is set to Master. h Set the clock mode to Both Edges.
Chapter 5: Troubleshooting To test the cables Adjust sampling positions using Eye Finder 1 Select the Sample Positions button. The Eye Finder window will appear. 2 In the “Buses/Signals” section of the Eye Finder window, ensure that the check box next to “My Bus 1” is checked. 3 Drag the blue bar for “My Bus 1” to approximately -3 ns. 4 Select the plus sign to expand bus “My Bus 1”. 5 Select the Run button in the Eye Finder window. 6 Ensure that an eye appears for each bit.
Chapter 5: Troubleshooting To test the cables region. If not, see “To re-align a stray channel” on page 46. 7 Select OK to close the Sample Positions window. 8 Select OK to close the Analyzer Setup window. 9 Switch to the Listing window by selecting the Listing tab at the bottom of the main window. 10 Select the Run icon . 11 Data will appear in the Listing Window upon completion of the run. 12 If the listing shows that the data alternates between AAAA and 5555, then the probe and cable pass the test.
Chapter 5: Troubleshooting To test the cables Connect and configure the logic analyzer to test other pods 1 Disconnect all flying lead probes from the 2 x 9 test fixtures. 2 Connect the second E5383A Flying Lead Probe set to the next pod to be tested. NOTE: In this example the pod to be tested will be Pod 2. 3 Connect the even bits of Pod 2 to the 2 x 9 test fixture at the pulse generator’s OUTPUT 2. 4 Connect the odd bits of Pod 2 to the 2 x 9 test fixture at the pulse generator’s OUTPUT 2.
Chapter 5: Troubleshooting To test the cables 11 Move the starting position to -3 ns. 12 Run Eye Finder and ensure that an eye is found for each bit. 13 Select OK to close the Eye Finder window. 14 Select OK to close the Analyzer Setup window. 15 Switch to the Listing window and run the logic analyzer. 16 Examine the listing. If the listing shows that the data alternates between 0 AAAA and 1 5555 (or AAAA and 5555 if the pod does not have a clock bit), then the probe and cable pass the test.
Chapter 5: Troubleshooting To test the cables 18 Return to the troubleshooting flow chart.
6 Replacing Assemblies This chapter contains the instructions for removing and replacing the logic analyzer module, the circuit board of the module, and the probe cables of the module as well as the instructions for returning assemblies.
Chapter 6: Replacing Assemblies CAUTION: Turn off the mainframe before installing, removing, or replacing a module. CAUTION: Electrostatic discharge can damage electronic components. Use grounded wrist-straps, mats, and standard ESD precautions when you perform any service to the mainframe or the modules in it. Tools Required • A T10 TORX screwdriver is required to remove screws that hold the probe cables to the back panel.
Chapter 6: Replacing Assemblies To remove the logic analyzer cable 1 Remove power from the instrument a In the session manager, select Shutdown. b At the query, select Power Down. c When the “OK to power down” message appears, turn the instrument off. d Disconnect the power cord. 2 Remove the logic analyzer cable. a Use a T10 Torx driver to remove the screws that secure the logic analyzer cable to the rear panel. b Gently lift the logic analyzer cable end connector from the circuit board connector.
Chapter 6: Replacing Assemblies To install the logic analyzer cable 1 Connect the logic analyzer cable to the logic analyzer circuit board. a Align the logic analyzer cable end connector with the circuit board cable connector and gently apply pressure to seat the logic analyzer cable onto the circuit board connector. 2 Secure the cable to the rear panel. a Install the T10 screws (two per cable) and tighten to 5 in/lb. CAUTION: If you over tighten the screws, damage to the rear panel may occur.
Chapter 6: Replacing Assemblies To replace the circuit board 1 Remove the logic analyzer cables using the “To remove the logic analyzer cable” procedure on page 85. 2 Remove the four screws attaching the ground spring and back panel to the circuit board, then remove the back panel and the ground spring. 3 Replace the faulty circuit board with a new circuit board. On the faulty board, make sure the 2x15 (30-pin) ribbon cable is connected between J15 and J12.
Chapter 6: Replacing Assemblies To return assemblies Before shipping the module to Agilent Technologies, contact your nearest Agilent Technologies Sales Office for additional details. Information on contacting Agilent can be found at http://www.agilent.com. 1 Write the following information on a tag and attach it to the module. • Name and address of owner • Model number • Serial number • Description of service required or failure indications 2 Remove accessories from the module.
7 Replaceable Parts This chapter contains information for identifying and ordering replaceable parts for your module.
Chapter 7: Replaceable Parts Ordering Replaceable Parts To order a part, visit us on the web at www.parts.agilent.com or call us in the United States at 1-877-447-7278. Or you can contact your nearest Agilent Technologies Sales Office for assistance. Exchange assemblies Some assemblies are part of an exchange program with Agilent Technologies. The exchange program allows you to exchange a faulty assembly with one that has been repaired and performance verified by Agilent Technologies.
Chapter 7: Replaceable Parts Replaceable Parts List The replaceable parts list is organized by reference designation and shows exchange assemblies, electrical assemblies, then other parts.
Chapter 7: Replaceable Parts Replaceable Parts Ref. Des. Agilent Part Number QTY Description Exchange Assemblies 16910-69501 Replacement Assemblies A1 16910-66501 1 Acquisition Board Assembly H1 16903-68713 2 H1 16900-68713 2 H2 0515-2306 4 H3 0515-0430 3 H4 16715-29101 1 Replacement Thumb Screws with Sleeve, 2 sets Replacement Thumb Screws with Sleeve, 6 sets MSPH M3.0 x 0.5 10 mm T10 (Cable to Rear Panel) MSPH M3.0 x 0.
Chapter 7: Replaceable Parts Replaceable Parts Ref. Des.
Chapter 7: Replaceable Parts 16910A Exploded View Exploded view of the 16910A logic analyzer 94
Chapter 7: Replaceable Parts 16911A Exploded View Exploded view of the 16911A logic analyzer 95
Chapter 7: Replaceable Parts 96
8 Theory of Operation This chapter presents the theory of operation for the logic analyzer card.
Chapter 8: Theory of Operation The information in this chapter is to help you understand how the logic analyzer operates. This information is not intended for component-level repair. Block-Level Theory The block diagram of the 16910/11A logic analyzer is shown below.
Chapter 8: Theory of Operation Probes. The 16910A logic analyzer card contains 6 probe pods; the 16911A contains 4 probe pods. Each pod is comprised of one cable and contains 16 single-ended data channels, a clock channel, two serial I2C programming lines for configuring analysis probes, +5 V for powering analysis probes, and 22 ground signals. Each cable has a 40-pin probe cable connector. The pods provide +5 Vdc ±5% auxiliary power to each 40-pin probe cable connector.
Chapter 8: Theory of Operation onto the card and provides for control of the card by the analyzer mainframe. It also provides a path for unloading acquired data to the analyzer display. The FPGA converts bus signals generated by the mainframe processor into control signals for the logic analyzer card. It also provides centralized functions for the card such as I2C, Calibration signals, Flag routing, and Timing mode sample clock.
Index A accessories, 10 acquisition, 67 assemblies exchange, 90 return, 88 B block-level theory, 98 C cable install, 86 remove, 85 test E5379A cable, 73 calibrating see also testing performance calibration, 61 strategy, 62 characteristics environmental, 12 circuit board replace, 87 clean module, 17 cleaning the instrument, 103 configure one-card module, 17 connectors, test, 22, 71 E environment characteristics, 12 operating, 16 equipment test, 13, 21 exchange assemblies, 90 eye finder, 44, 78 adjusting, 44
Index 102
Safety Notices This apparatus has been designed and tested in accordance with IEC Publication 1010, Safety Requirements for Measuring Apparatus, and has been supplied in a safe condition. This is a Safety Class I instrument (provided with terminal for protective earthing). Before applying power, verify that the correct safety precautions are taken (see the following warnings). In addition, note the external markings on the instrument that are described under "Safety Symbols.
Notices © Agilent Technologies, Inc. 20012004 No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Agilent Technologies, Inc. as governed by United States and international copyright laws. Manual Part Number 16910-9700, April 2004 Print History 16910-97000, April 2004 Agilent Technologies, Inc.
