Specifications

5-22
As a result of extremely high integration of logic LSIs using MOS FETs, the thickness of the MOS
FETs’ gate oxide layer is becoming thinner (less than 2.0 nm), and such MOS FETs have been pro-
duced recently. In evaluating these kinds of MOS FETs, leakage current becomes larger by the tun-
neling effect. Since the MOS gate capacitance has high impedance, most of the test signal's current
flows as leakage current. Consequently, the C-V characteristic of MOS FET with a thin gate oxide
layer cannot be measured accurately. To solve this problem, the test frequency should be set higher
(1 MHz or more) than usual to reduce the capacitive impedance across the thin gate oxide layer to
as low as possible. It is also important to simplify the measurement configuration to reduce residu-
als that exist in the measurement path. If you perform high-frequency C-V measurement using the
4TP configuration, the measurement error increases due to the residual inductance of the cable that
is connected between the guard electrodes of probe heads. Also, the compensation does not work
properly because the distance between probes easily varies. To solve this problem, a simplified 2T
configuration with the 42941A impedance probe, as shown in Figure 5-32, is highly recommended
for accurate high-frequency C-V measurement.
Note: Agilent offers an advanced C-V measurement solution for the ultra-thin gate oxide layer that
uses the Agilent 4294A LF impedance analyzer. To eliminate the effects of tunneling leakage
current, the MOS gate capacitance is calculated from the result of swept frequency impedance
measurement (|Z| – q) at multiple DC bias points. (Refer to Application Note 4294-3,
Evaluation of MOS Capacitor Oxide C-V Characteristics Using the Agilent 4294A, literature
number 5988-5102EN.)
Figure 5-32. Example of high-frequency C-V measurement system configuration