Specifications

5-20
5.6 Silicon wafer C-V measurement
The C-V (capacitance versus DC bias voltage) characteristic of a MOS structure is an important mea-
surement parameter for evaluating silicon wafers. To evaluate the capacitance that varies with
applied DC bias voltage, capacitance is measured at a low AC signal level while sweeping a number
of bias voltage points. Because the device usually exhibits a low capacitance (typically in the
low picofarads), the instrument must be able to measure low capacitance accurately with a high
resolution at a low test signal level. Precise bias voltage output is also required for accurate C-V
measurement. Typical C-V measurement conditions are listed in Table 5-2. Auto-balancing bridge
instruments are usually employed to satisfy the required performance.
Figures 5-30 and 5-31 show measurement setup examples using the auto-balancing bridge instrument
(Agilent 4294A, E4980A, etc.) with a wafer prober station. Since the Low terminal of the auto-bal-
ancing bridge instrument is sensitive to incoming noise, it is important that the Low terminal not be
connected to the substrate that is electrically connected to the prober’s noisy ground. If the wafer
chuck (stage) of the prober is isolated from the ground and effectively guarded, the shielding con-
ductor of the 4TP cable can be connected to the prober’s guard terminal to minimize stray capaci-
tance around the probes.
When a device with low resistivity is measured, applied DC voltage decreases due to DC leakage cur-
rent through the device, and this may cause C-V measurement error. Using the DC bias auto level
control (ALC) function helps to lessen this problem.
Table 5-2. Typical C-V measurement conditions
Frequency 10 kHz to 1 MHz
(10 kHz to 100 MHz for a thin gate oxide layer measurement)
Capacitance range 0.0001 to 1000 pF
Capacitance accuracy ±0.1%
Test signal level 20 or 30 mVrms typical
DC bias voltage 0 to ± 40 V
Bias voltage resolution ≤ 10 mV
Bias voltage accuracy ±0.1%