Specifications

5-19

5.5 MOS FET measurement

Evaluating the capacitances between the source, drain, and gate of an MOS FET is important in the

design of high frequency and switching circuits. Generally, these capacitances are measured while a

variable DC voltage source is connected to the drain terminal referenced to the source, and the gate

is held at zero DC potential (Figure 5-28). When an instrument is equipped with a guard terminal

and an internal DC bias source, capacitances Cds, Cgd, and Cgs can be measured individually.

Figures 5-29 (a) through (c) show the connection diagrams for an instrument’s High, Low, and

Guard terminals. The guard is the outer conductors of BNC connectors of the UNKNOWN terminals.

The E4980A, with Option E4980A-001 has an independent DC source in addition to an internal DC

bias and allows the Cgs measurement set up to be simplified as sown in Figure 5-29 (d).

Figure 5-28. Capacitance of MOS FET

Figure 5-29. MOS capacitance measurement

High

Low

Guard

Cgs

DC source

Typical values (for 1 MHz measurement):

C: 1 µF L: 100 µH

(d) Cgs measurement using the E4980A

with Option E4980A-001