Service manual

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the ac line-synchronization signal derived from the Bias Supply circuits. TRIG_IN is derived from the external trigger
signal connected to the rear panel. GET is received directly from the GPIB. P_TRIG* is generated in the primary
microprocessor from either the *TRG or TRIG commands received via the GPIB. The Trigger Generator circuit includes
the internal timer, which generates trigger signals from the clock (E) and frequency select (FSEL) signals. The Trigger
Generator selects between TRIG* and the timer signal to produce the PRI_TRIG signal, which is sent to the modules. A
trigger signal is also supplied to the rear-panel TRIGGER OUT connector for use with external equipment.
The Fan Supply And Speed Control circuit varies the fan speed as required to provide adequate cooling for the number of
modules installed and the power to be dissipated, while minimizing noise.
The Load Modules Interface circuit connects the selected module to the SER_OUT and SER_IN ports of the primary
microprocessor. This circuit also informs the microprocessor how many modules are installed in the mainframe. A further
description is provided at the end of this chapter.
Control Board Circuits
Signals between the mainframe GPIB Board and the module Control Board are connected via ribbon cables across the top
edges of each board to optocouplers on the Control Board. These optocouplers, and the transformer in the Secondary Bias
Supply, provide isolation between the chassis-ground referenced circuits in the mainframe and the circuits in the load
modules, each of which is referenced to its own - Input.
The Secondary Microprocessor associated with each module controls the operation of the module. It translates the serial
data received from the Primary Microprocessor into a parallel data bus and other control signals. Values are loaded into the
Main DAC, Transient DAC, Transient Generator, and Readback DAC via the data bus. The Secondary Microprocessor
circuits contain an EEPROM which stores the module's min/max values, ranges, and other information, as well as
calibration constants.
The DAC Reference Select circuit enables one voltage - IMON*, VMON*, or -10V_REF to be the VREF supplied to the
Main DAC and Transient DAC. Which reference is used depends on the operating mode and range.
Transient operation causes the input power stages to switch between two load levels. The Transient Generator uses the
frequency select (FSEL) and clock (E) signals from the microprocessor to generate the timing signal, HIGH*, which opens
and closes the solid-state switch in the output of the Transient DAC circuit. The outputs of the Main DAC, the Transient
DAC, and the EXT_PROG signal from the rear-panel connector are summed to produce SLEW.
In transient operation, SLEW has a step change from the main value to the transient value and back again, at a frequency
controlled by the Transient Generator. RC networks in the Slew Rate Control circuit integrate the step changes in
accordance with the programmed slew rate to allow a controlled transition from one load setting to another.
Solid-state switches in the output of the Slew Rate Control circuit determine if the programming signal becomes CV_PROG
or CC_PROG.
Also located on the Control Board are the Readback DAC and Readback Comparators. Input voltage, input current, and
heatsink temperature are read by successive approximation. The Readback DAC and comparator also return a test signal to
the microprocessor during selftest to determine if the DAC circuits are operating properly.
The input voltage and current monitor signals, VMON and IMON, are buffered and connected to the rear-panel terminal
strip.