Operating instructions

Status Reporting

Status Byte Register

The Status Byte register summarizes all of the status events from all status registers. Table 5-5 describes the status events

that apply to the electronic load.

The Status Byte register can be read with a serial poll or *STB? query. When a serial poll is sent in response to a service

request, Bit 6 of the Status Byte register will contain the RQS bit. The RQS bit is the only bit that is automatically cleared

after a serial poll. The other bits in the Status Byte register (including the MSS bit) are unaffected by a serial poll.

When the Status Byte register is read with a *STB? query, Bit 6 of the Status Byte register will contain the MSS bit. The

MSS bit indicates that the load has at least one reason for requesting service. It is the inclusive-OR of the enabled bits

(excluding bit 6) of the Status Byte register. *STB? does not affect the status byte. The Status Byte register is cleared

when a *CLS command clears all of the associated status registers.

Service Request Enable Register

The Service Request Enable register can be programmed to specify which bits in the Status Byte register will generate

service requests. All bits except Bit 6 (RQS/MSS) can be enabled to generate service requests. In addition to generating a

service request, the enabled bits in the Service Request Enable register are logically-ORed to become the MSS bit in the

Status Byte register.

Note The present settings of the Service Request Enable register can be saved in non-volatile memory if

*PSC is programmed to zero. The next time the unit is turned on, the Service Request Enable register

will be programmed according to the saved settings.

Table 5-5. Status Byte Bit Description

Mnemonic Bit

Value Meaning

CSUM 2 4 Channel Summary. Indicates if an enabled channel event has occurred. Affected by

Channel Condition, Channel Event, and Channel Summary Event registers.

QUES 3 8 Questionable. Indicates if an enabled questionable event has occurred. Affected by

Questionable Condition and Questionable Event registers.

MAV 4 16 Message Available. Indicates if the Output Queue contains data.

ESB 5 32 Event Status Bit. Indicates if an enabled standard event has occurred. Affected by

Standard Event register.

RQS/MSS 6 64

During a serial poll, RQS (Request Service)) is returned and cleared. For an *STB?

query, MSS (Master Summary Status) is returned without being cleared.

OPER 7 128 Operation. Indicates if an enabled operation event has occurred. Affected by

Operation Condition and Operation Event registers.

Bits 0 and 1 are not used by the electronic load. They will be read back as zeroes.