Operating instructions

Status Reporting
86
Table 5-1. Channel Status Bit Description (continued)
Mnemonic Bit
1
Value Meaning
OT 4 16 Overtemperature. An overtemperature condition has occurred on a
channel. When this occurs, both Bit 4 and Bit 13 (PS bit) are set and the
channel is turned off. Bits 4 and 13 remain set until the channel (or unit)
has cooled down well below the overtemperature trip point and
INP:PROT:CLE is programmed.
EPU 9 512 Extended Power Unavailable. This bit has no significance in later "A"
version and in all ’’B’’ version electronic loads.
UNR 10 1024 Unregulated Input. A channel is unregulated. This condition sets Bit 10.
When the load becomes regulated, Bit l0 is cleared. Unregulated input
does not occur in CV mode or in the 1 ohm range of CR mode.
RV 11 2048 Reverse Voltage on input. A channel has a reverse voltage applied to it.
When this occurs, both Bit 11 and Bit 0 (VF bit) are set. When the reverse
voltage is removed, Bit 11 is cleared. However, Bit 0 remains set until
INP:PROT:CLE is programmed.
OV 12 4096 Overvoltage. An overvoltage condition has occurred on a channel. When
this occurs, both Bit 12 and Bit 0 (VF bit) are set and the FETs are turned
on as hard as possible to lower the voltage. Bits 12 and 0 remain set until
the overvoltage condition is removed and INP:PROT:CLE is
programmed.
PS 13 8192 Protection Shutdown. A channel has turned off because of an overcurrent,
overpower, or overtemperature condition. When any of these three
conditions occur, Bit 13 is set and remains set until INP:PROT:CLE is
programmed.
1
Bits 2, 5-8, 14 and 15 are not used by the electronic load.
Questionable Status
The Questionable Status registers inform you that one or more questionable status conditions, which indicate the presence
of certain errors or faults, have occurred on at least one channel. This lets you check for specific errors or faults that have
occurred without having to poll each channel individually. Table 5-2 lists the questionable status conditions that apply to
the electronic load. These conditions are the same as the channel status conditions. Refer to Table 5-1 for a complete
description.
The Questionable Status Condition register represents the present status of all channel conditions; the bits are set when the
indicated condition is true.
The Questionable Status Event register represents all of the conditions that have occurred since the last time this register
was read. A condition transition from 0-to-1 on a bit in the Questionable Status Condition register will set the
corresponding bit in the Questionable Status Event register. Reading the Questionable Status Event register resets it to
zero.
The Questionable Status Enable register can be programmed to specify which questionable status event bits are logically-
ORed to become Bit 3 (QUES bit) in the Status Byte register.