Programming instructions
Table Of Contents
- Contents
- Title Page
- Chapter 1 Introduction to Programming
- Chapter 2 Programming Getting Started
- Chapter 3 Programming over HP-IB
- Chapter 4 Programming over RS-232-C
- Chapter 5 Programming and Documentation Conventions
- Chapter 6 Status Reporting
- Figure 6-1. Status Reporting Overview Block Diagram
- Table 6-1. Status Reporting Bit Definition
- Status Reporting Data Structures
- Status Byte Register (SBR)
- Service Request Enable Register (SRER)
- Trigger Event Register (TRG)
- Standard Event Status Register (SESR)
- Standard Event Status Enable Register (SESER)
- User Event Register (UER)
- Local Event Register (LCL)
- Operation Status Register (OPR)
- Limit Test Event Register (LTER)
- Mask Test Event Register (MTER)
- Histogram Event Register (HER)
- Arm Event Register (ARM)
- Error Queue
- Output Queue
- Message Queue
- Key Queue
- Clearing Registers and Queues
- Figure 6-3. Status Reporting Decision Chart
- Chapter 7 Installing and Using the Programmer's Reference
- Chapter 8 Programmer’s Quick Reference
- Warranty
- Index
Mask Test Event Register (MTER)
Bit 0 (COMP) of the Mask Test Event Register is set when the Mask Test
completes. The Mask Test completion criteria are set by the MTESt:RUMode
command.
Bit 1 (FAIL) of the Mask Test Event Register is set when the Mask Test fails.
This will occur whenever any sample is recorded within any polygon defined
in the mask.
The Mask Test Event Register is read and cleared with the MTER? query.
When either the COMP or FAIL bits are set, they in turn set the MASK bit
(bit 10) of the Operation Status Register. You can mask the COMP and FAIL
bits, thus preventing them from setting the MASK bit, by defining a mask
using the MTEE command.
Enable Mask Value
Block COMP and FAIL 0
Enable COMP, block FAIL 1
Enable FAIL, block COMP 2
Enable COMP and FAIL 3
Status Reporting
Mask Test Event Register (MTER)
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