Programming instructions
Table Of Contents
- Contents
- Title Page
- Chapter 1 Introduction to Programming
- Chapter 2 Programming Getting Started
- Chapter 3 Programming over HP-IB
- Chapter 4 Programming over RS-232-C
- Chapter 5 Programming and Documentation Conventions
- Chapter 6 Status Reporting
- Figure 6-1. Status Reporting Overview Block Diagram
- Table 6-1. Status Reporting Bit Definition
- Status Reporting Data Structures
- Status Byte Register (SBR)
- Service Request Enable Register (SRER)
- Trigger Event Register (TRG)
- Standard Event Status Register (SESR)
- Standard Event Status Enable Register (SESER)
- User Event Register (UER)
- Local Event Register (LCL)
- Operation Status Register (OPR)
- Limit Test Event Register (LTER)
- Mask Test Event Register (MTER)
- Histogram Event Register (HER)
- Arm Event Register (ARM)
- Error Queue
- Output Queue
- Message Queue
- Key Queue
- Clearing Registers and Queues
- Figure 6-3. Status Reporting Decision Chart
- Chapter 7 Installing and Using the Programmer's Reference
- Chapter 8 Programmer’s Quick Reference
- Warranty
- Index
User Event Register (UER)
This register hosts the LCL bit (bit 0) from the Local Event Register. The
other 15 bits are reserved. You can read and clear this register using the
UER? query. This register is enabled with the UEE command. For example, if
you want to enable the LCL bit, you send a mask value of 1 with the UEE
command; otherwise, send a mask value of 0.
Local Event Register (LCL)
This register sets the LCL bit in the User Event Register and the USR bit (bit
1) in the status byte. It indicates a remote-to-local transition has occurred.
The LER? query is used to read and to clear this register.
Operation Status Register (OPR)
This register hosts the WAIT TRIG bit (bit 5), the LTEST bit (bit 8), the
HIST bit (bit 9), the MASK bit (bit 10), and the PROG bit (bit 14).
•
The WAIT TRIG bit is set by the Trigger Armed Event Register and
indicates that the trigger is armed.
•
The LTEST bit is set when a limit test fails or is completed and sets the
corresponding FAIL or COMP bits in the Limit Test Event Register.
•
The HIST bit is set when the COMP bit is set in the Histogram Event
Register, indicating that the histogram measurement has satisfied the
specified completion criteria.
•
The MASK bit is set when the Mask Test either fails specified conditions or
satisfies its completion criteria, setting the corresponding FAIL or COMP
bits in the Mask Test Event Register.
•
The PROG bit is reserved for future use.
•
If any of these bits are set, the OPER bit (bit 7) of the Status Byte Register
is set. The Operation Status Register is read and cleared with the OPER?
query. The register output is enabled or disabled using the mask value
supplied with the OPEE command.
Status Reporting
User Event Register (UER)
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