Instruction manual

Chapter 3 Programming Your Counter for Remote Operation

Status Reporting

3-28 Programming Guide

A detailed description of each bit in the Status Byte Register follows:

• Bits 0 - 1 are not used.

• Bit 2 (EAV) Summarizes the Error/Event Queue.

This bit is set when the Error/Event Queue is not empty.

• Bit 3 (QSB) summarizes the Questionable Data Status Event

This bit indicates whether or not one or more of the enabled

Questionable Data events have occurred since the last reading or

clearing of the Questionable Data Status Event Register.

This bit is set TRUE (one) when an enabled event in the Questionable

Data Status Event Register is set TRUE. Conversely, this bit is set

FALSE (zero) when no enabled events are set TRUE.

• Bit 4 (MAV) (Message AVailable) summarizes the Output Queue.

This bit indicates whether or not the Output Queue is empty.

This bit is set TRUE (one) when the Counter is ready to accept a

request by the external computer to output data bytes; that is, the

Output Queue is not empty. This bit is set FALSE (zero) when the

Output Queue is empty.

Table 3-4. Status Byte Register

BIT WEIGHT SYMBOL DESCRIPTION

— — Not used

4 EAV Error/Event Queue Not Empty

8 QSB

Questionable Data/Signal Status Register

Summary Bit

16 MAV Message Available Summary Bit

32 ESB Standard Event Status Register Summary Bit

64 RQS/MSS Request Service/Master Status Summary Bit

128 OSB Operation Status Register Summary Bit