User`s guide

6-13

Status Reporting

Operation Status Register (OPR)

This register hosts the RUN bit (bit 3), the WAIT TRIG bit (bit 5), and the OVLR

bit (bit 11).

• The RUN bit is set whenever the instrument is not stopped.

• The WAIT TRIG bit is set by the Trigger Armed Event Register and indicates

that the trigger is armed.

• The OVLR bit is set whenever a 50Ω input overload occurs (54640-series

only)

• If any of these bits are set, the OPER bit (bit 7) of the Status Byte Register

is set. The Operation Status Register is read and cleared with the OPER?

query. The register output is enabled or disabled using the mask value

supplied with the OPEE command.

Arm Event Register (ARM)

This register sets bit 5 (Wait Trig bit) in the Operation Status Register and the

OPER bit (bit 7) in the Status Byte Register when the instrument becomes

armed.

The ARM event register stays set until it is cleared by reading the register with

the AER? query or using the *CLS command. If your application needs to detect

multiple triggers, the ARM event register must be cleared after each one.

If you are using the Service Request to interrupt a program or controller

operation when the trigger bit is set, then you must clear the event register after

each time it has been set.