Specifications

83
Chapter 3: Testing Performance
To Test the Single-clock, Multiple-edge, State Acquisition
To Test the Single-clock, Multiple-edge, State
Acquisition
Testing the single-clock, multiple-edge, state acquisition verifies the performance
of the following specifications:
• Minimum master to master clock time
• Maximum state acquisition speed
•Setup/Hold time
This test checks a combination of data channels using a multiple-edge single
clock at two selected setup/hold times.
Equipment Required
Set up the equipment
1 If you have not already done so, do the procedure “To Set up the Test
Equipment and the Analyzer” on page 38. Use the pulse generator settings
listed below.
2 Make the following changes to the pulse generator configuration.
(TXLSPHQW &ULWLFDO6SHFLILFDWLRQV
5HFRPPHQGHG+3
$JLOHQW0RGHO3DUW
3XOVH*HQHUDWRU 0K]QVSXOVHZLGWKSVULVHWLPH $RSWLRQ
'LJLWL]LQJ2VFLOORVFRSH ≥*+]EDQGZLGWKSVULVHWLPH $Z$
$GDSWHU 60$P%1&I 
60$&RD[&DEOH4W\ 
&RXSOHU4W\ %1&PP 
%1&7HVW&RQQHFWRU[4W\
7LPHEDVH &KDQQHO
3HULRGQV 'LYLGH38/6(÷
:LGWKQV