Specifications

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Chapter 3: Testing Performance
To Test the Multiple-clock, Multiple-edge, State Acquisition
9 Select the clock combination to be tested.
a In the Analyzer setup window, select the Sampling tab.
b Under the Sampling tab, select the clock edge field under each clock.
Then select Falling Edge. The clock setup field should show J↓ + K↓ +
L↓ + M↓.
10 Verify the test data.
a In the Listing window, select Run. The display should show an
alternating pattern of “AA” and “55”.
b If the “Pattern NOT found for marker...” error message does not appear,
then the test passes. Record the Pass or Fail in the performance test
record.
11 Repeat steps 9 and 10 for the next clock combination listed in the table in
step 9, until both clock combinations have been tested.
12 If the setup/hold used for the previous steps was 5.0/-2.0 ns, repeat steps 1
through 11 using setup/hold -1.5/4.5 ns. If the setup/hold used for the
previous steps was -1.5/4.5 ns, continue on with the next section.