Specifications

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Chapter 3: Testing Performance
To Test the Multiple-clock, Multiple-edge, State Acquisition
Check the setup/hold with single clock edges, multiple
clocks
1 Select the logic analyzer setup/hold time.
a In the Analyzer setup window, select the Sampling tab.
b Under the Sampling tab, select and activate any two clock edges.
You must have two single-edge clocks selected before the Setup/Hold window will
allow a Setup/Hold of 5.0/-2.0 ns.
c Select the Format tab. Under the Format tab, select Setup/Hold.
d In the Setup and Hold window, ensure All bits is selected.
e Enter the setup time of the setup/hold combination to be tested in the
Setup: field.
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f Select the close (X) button in the upper-right corner to close the Setup/
Hold window.
2 Disable the pulse generator channel 1 COMP (LED off).