Specifications

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Chapter 3: Testing Performance
To Test the Single-clock, Single-edge, State Acquisition
Check the setup/hold combination
1 Select the logic analyzer setup/hold time.
a In the Analyzer setup window, select the Format tab.
b Under the Format tab, select Setup/Hold.
c In the Setup and Hold window, ensure All bits is selected.
d Enter the setup time of the setup/hold combination to be tested in the
Setup: field.
Setup/Hold Combinations
QV
QV
e Select the close (X) button in the upper-right corner to close the Setup/
Hold window.
2 Disable the pulse generator channel 1 COMP (LED off).