Specifications

166
Index
T
test
0V user threshold, 46
analyzer chip memory bus
, 160
analyzer memory bus SU/H measure
,
160
cables
, 133
calibration
, 161
chip registers
, 160
comparators
, 161
connectors, 35
CPLD register
, 158
ECL threshold
, 43
equipment, 13, 32, 38
FPGA load
, 158
FPGA register
, 158
global and local arm lines, 161
HW assisted memory cell
, 159
inter-chip resource bus
, 161
inter-module flag bits, 161
interval
, 32
master controller
, 162
memory address bus, 159
memory data bus
, 158
memory DMA unload
, 159
memory sleep mode, 159
memory unload modes
, 159
module
, 28
multi-card module, 32, 105
multiple-clock, multiple-edge, state
acquisition
, 66
one-card module, 32
performance record
, 121
pod
, 47
power, 33, 138
record description
, 32
self-test
, 33, 131
single-clock, multiple-edge, state
acquisition
, 83
single-clock, single-edge, state
acquisition
, 48
strategy
, 32
system
, 132
system backplane clock, 160
system clocks
, 160
threshold accuracy
, 40
time interval accuracy, 98
zoom acquisition
, 162
zoom data lines
, 162
zoom FISO redundancy, 162
test and clock synchronization circuit
,
156, 158
test signal
, 56, 74, 91, 113
testing performance
, 31
equipment
, 13, 32, 38
interval
, 32
multi-card module
, 32, 105
multiple-clock, multiple-edge, state
acquisition
, 66
single-clock, multiple-edge, state
acquisition
, 83
single-clock, single-edge, state
acquisition
, 48
threshold accuracy
, 40
time interval accuracy
, 98
theory of operation, 153
threshold
, 158
0V user
, 46
accuracy, 40
data
, 156
ECL
, 43
time interval accuracy, 98
tools required
, 140
troubleshooting
, 127
V
VRAM
parallel data bus
, 161
Z
zoom
acquisition
, 162
controller data lines
, 162
FISO redundancy
, 162
master controller, 162