Specifications

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Chapter 8: Theory of Operation
to see if self-calibration was successful.
Passing the Calibration Test implies that the module can reliably perform an
operation accuracy self-calibration every time Run is selected. Consequently the
incoming data is optimized to reduce channel-to-channel skew so the acquisition
ICs can reliably capture the incoming data.
Zoom Data Lines Test. The Zoom Data Lines Test verifies the 2GHz
TimingZoom controller data path. A test pattern is written to a counter register in
the zoom controller. The counter register is decremented using a system clock
while counting each system clock pulse. When the register reaches “0”, the
register decrement is halted. The system clock count is then compared with the
initial register data pattern. This process is repeated for a number of register test
patterns.
Passing the Zoom Data Lines Test implies that the counter register in the zoom
controller can be written to, and that the data path to the zoom controller is
reliable.
Zoom Master Controller Test. The Zoom Master Controller Test verifies the
zoom controller circuit on the master board. The test is similar to the Zoom
Controller Data Lines Test, except a divider ratio is configured to decrement the
counter register a number of times for each system clock pulse.
Passing the Zoom Master Controller Test implies that the 2GHz TimingZoom
controller on the master board is operating properly.
Zoom FISO Redundancy Test. The Zoom FISO Redundancy Test verifies the
2GHz TimingZoom acquisition memory. The FISOs are put into a self-test mode,
which clocks test patterns into FISO memory. The FISO memory is then
downloaded and compared with known values. Additionally, if bad memory
locations are found, a redundancy routine is initiated to replace bad memory
locations with a redundant memory location.
Passing the Zoom FISO Redundancy Test implies each memory location in the
2GHz TimingZoom acquisition memory can store a logic “0” and logic”1”.
Zoom Acquisition Test. The Zoom Acquisition Test verifies the data inputs to
the 2GHz TimingZoom acquisition memory and that the TimingZoom acquisition
clock is at the correct sampling frequency. Test data is created by clocking the
comparators test port. A TimingZoom acquisition is made, and 16k samples
downloaded. The patterns are compared with known values. Additionally, data
transition edges are counted and compared with a known value.
Passing the Zoom Acquisition Test implies that the 2GHz Timing Zoom circuit is
operating properly, and that a TimingZoom acquisition reliably captures
acquisition data.