Specifications

161
Chapter 8: Theory of Operation
that the procedure to test the Time Interval Accuracy in Chapter 3 provides a
more reliable characterization of clock oscillator drift.
Comparators Test. The Comparators Test ensures the data signal comparators
in the module front end can be set to their maximum and minimum thresholds,
and that they recognize activity at the signal inputs. A clock signal is routed to a
test port on each comparator. The threshold is then set to the minimum value.
The comparator output is then read, and compared with a known value. The
threshold is then set to a maximum value. The comparator output is again read,
and compared with a known value.
Passing the Comparators Test implies that the front end comparators are
operating properly, can recognize both a logic “0” and logic “1”, and can properly
send the acquisition data downstream to the acquisition ICs.
Inter-chip Resource Bus Test. The Inter-chip Resource Bus Test verifies the
resource lines that run between each acquisition IC to ensure that the resource
lines can be both driven as outputs and read as inputs. The resource registers are
written with test patterns, read back, then compared with known values. The
resource registers are then written with test patterns, read back from a different
acquisition IC, and then compared with known values.
Inter-module Flag Bits Test. Flag bits are used for module-to-module
communication within the 16700-series system. The Inter-module Flag Bits Test
verifies that the flag bit lines can be driven and received by each acquisition IC in
each module. Test patterns are written to the flag registers, read by the other
acquisition ICs in the other modules, and then compared with known values.
Passing the Inter-module Flag Bits Test implies that the acquisition ICs can
communicate using Flag Bits through the CPU interface and the 16700-series
backplane, and that the operations utilizing the flag bits can be properly
recognized by all modules in the system.
Global and Local Arm Lines Test. The Global and Local Arm Lines Test
verifies that the local arm signal can be received by each acquisition IC on the
master board. The test also verifies the global arm signal can be driven by each
acquisition IC on a master board, and received by all acquisition ICs in the
module on the master and on all expander boards. The arm lines are asserted and
read at the acquisition ICs to ensure each acquisition IC recognizes the signal.
Passing the Global and Local Arm Lines Test implies any acquisition ICs on the
master board can arm the module, and that all acquisition ICs can recognize the
arm signal.
Calibration Test. The Calibration Test ensures that each acquisition IC in the
module can perform an operational accuracy self-calibration every time Run is
selected. The module is set in various configurations, after which the self-
calibration routing is initiated. The results of the self-calibration is then checked