Specifications

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Chapter 8: Theory of Operation
Chip Registers Read/Write Test. The Chip Registers Read/Write Test verifies
that the registers of each acquisition IC are operating properly. Test patterns are
written to each register on each acquisition IC, read, and compared with known
values. The registers are reset, and verified that each register has been initialized.
Test patterns are then written to ensure the chip address lines are not shorted or
opened. Finally test data is written to registers of individual acquisition ICs to
ensure each acquisition IC can be selected independently.
Passing the Chip Registers Read/Write Test implies that the acquisition IC
registers can store acquisition control data to properly manage the operating of
each IC.
Analyzer Chip Memory Bus Test. The Analyzer Chip Memory Bus Test
verifies the operation of the acquisition memory buses between acquisition ICs.
After initializing the memory a walking “1” and “0” pattern is created at the
output of the acquisition ICs. This test data is stored in memory, read, and
compared with known values.
Passing the Analyzer Chip Memory Bus Test implies that the acquisition memory
buses between the acquisition ICs and acquisition memory is operating, and that
acquisition data can propagate from the ICs to memory.
System Clocks (Master/Slave/Psync) Test. The System Clocks (Master/
Slave/Psync) Test verifies the system clock are functional between all boards in a
master/expander multi-card module. The module is configured for a simple
measurement and test data is created. The test data is then downloaded and
compared with known values.
Passing the System Clocks (Master/Slave/Psync) Test implies that the acquisition
ICs of each expander board of a multi-card configuration can properly receive
system clocks, and that all acquisition ICs in the multi-card module will properly
capture data.
Analyzer Memory Bus SU/H Measure. The Analyzer Memory Bus SU/H
Measure is an internal test that ensures the timing between the acquisition IC and
acquisition memory is within acceptable parameters.
System Backplane Clock Test. The System Backplane Clock Test verifies the
100 MHz acquisition system clock. The test also ensures an on-board phase-
locked loop can properly generate multiples of the acquisition system clock
frequency. The 100 MHz acquisition system clock is first routed directly to the
acquisition ICs. A timer is initialized, run, and stopped after 100ms. the counter is
read, and compared with a known value. The acquisition system clock is then
routed to the phase-locked loop to generate a frequency of 166.7 MHz. Again, the
counter is initialized, run, and stopped after 100ms. The counter is read, and
compared with a known value.
Passing the System Backplane Clock Test implies that the system acquisition
clock is operating, and is within 5% of the desired acquisition frequency. Note