Specifications

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Chapter 8: Theory of Operation
Test and Clock Synchronization Circuit. The signals generated by the Test
and Clock Synchronization Circuit of the master card are sent to all expander
cards. Consequently, the Test and Clock Synchronization Circuit on each
expander card is disabled to allow the master-configured card to drive the
expander-configured card. The functionality of the Test and Clock
Synchronization Circuit remains the same, but the circuit drives up to 8 more
Acquisition IC and up to 16 more comparator test inputs.
Threshold. The thresholds of each of the expander card pods are individually
programmable, as with the master card pods. The threshold of the data and
clock/data channels of each pod is set to the same threshold voltage. The clock/
data channel on each pod of the expander card is available only as a data channel.
Self-Tests Description
The self-tests for the logic analyzer identify the correct operation of major
functional areas in the module.
CPLD Register Test. The CPLD Register Test verifies that the 16700-series
backplane can communicate with the 16740/41/42A module CDLP. The CPLD is
used to configure the backplane and the memory devices. The test is done using
both a walking “1” and walking “0” pattern. After the pattern has been stepped,
internal device registers are read.
Passing the CPLD Registers Test implies that the module backplane device can
be properly configured for module setup and data download.
Load FPGA Test. The Load FPGA Test verifies that the backplane interface
device and the data memory control device can be configured. Configuration data
is read from a file. During the configuration process, status signals are checked to
verify the 16740/41/42A module hardware is operating properly during the
configuration upload.
Passing the Load FPGA Test implies that the module can be properly configured
for normal operation.
FPGA Register Test. The FPGA Register Test verifies that the read/write
registers of the backplane interface device and the memory control device can be
written to then read. Both a walking “1” and “0” pattern is written to the device
registers. The registers are then read and compared with known values.
Passing the FPGA Registers Test implies that the module hardware configuration
can be properly managed as part of normal module operation.
Memory Data Bus Test. The Memory Data Bus Test verifies the read/write
access of the acquisition module from the system backplane. In addition, some of
the operations of the acquisition memory and control are also tested. A walking