Specifications

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Chapter 8: Theory of Operation
circuit controls RAM addressing during an acquisition run and during data upload
to the mainframe CPU.
Test and Clock Synchronization Circuit. ECLinPS (ECL in pico seconds) ICs
are used in the Test and Clock Synchronization Circuit for reliability and low
channel-to-channel skew. Test patterns are generated and sent to the
comparators during software operation verification (self-tests). The test patterns
are propagated across all data and clock channels and read by the acquisition ICs
to verify that the data and clock pipelines are operating correctly.
Also, the Test and Clock Synchronization Circuit generates a four-phase 125-MHz
sample/synchronization signal for the acquisition ICs operating in the timing
acquisition mode. At fast sample rates, the synchronizing signal keeps the
internal clocking of the individual acquisition ICs locked in step with the other
acquisition ICs in the module. At slower sample rates, one of the acquisition ICs
divides the 125-MHz clock signal to the appropriate sample rate. The slow speed
sample clock is then used by both acquisition ICs.
Clock and Data Threshold. The threshold circuit includes a precision octal
DAC and precision op amp drivers. Each of the eight channels of the DAC is
individually programmable which allows the user to set the thresholds of the
individual pods. The 16 data channels and the clock/data channel of each pod are
all set to the same threshold voltage.
CPU Interface. The CPU interface is a programmable logic device that converts
the bus signals generated by the microprocessor on the mainframe CPU card into
control signals for the logic analyzer card. All functions of the state and timing
card can be controlled from the backplane of the mainframe system including
storage qualification, sequencing, assigning clocks and qualifiers, RUN and STOP,
and thresholds. Data transfer between the logic analyzer card and the mainframe
CPU card is also accomplished through the CPU interface.
+5 VDC supply. The +5 VDC supply circuit supplies power to active logic
analyzer accessories such as preprocessors. Thermistors on the +5 VDC supply
lines and on the ground return line protect the logic analyzer and the active
accessory from overcurrent conditions. When an overcurrent condition is sensed,
the thermistors create an open that shuts off the current from the +5 VDC supply.
After a reset time of approximately 1 minute, the thermistor closes the circuit
and makes the supply current available.