Specifications

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Chapter 8: Theory of Operation
single ground. For applications where many channels are used (greater than
three) and signal risetimes are less than 3 ns, individual channel grounds should
be used.
The probe tip networks comprise a series of resistors (250 Ohm) connected to a
parallel combination of a 90 KOhm resistor and a 8.5 pF capacitor. The parallel 90
KOhm and 8.5 pF capacitor along with the lossy cable and terminations form a
divide-by-ten probe system. The 250 Ohm tip resistor is used to buffer (or raise
the impedance of) the 8.5 pF capacitor that is in series with the cable
capacitance.
Comparators. Two 9-channel comparators interpret the incoming data and
clock signals as either high or low, depending on where the user-programmable
threshold is set. The threshold voltage of each pod is individually programmed,
and the voltage selected applies to the clock channel as well as the data channels
of each pod.
Each of the comparators has a serial test input port used for testing purposes. A
test bit pattern is sent from the Test and Clock Synchronization Circuit to the
comparators. The comparators then propagate the test signal on each of the nine
channels of the comparator. Consequently, the operating system software can
test all data and clock channel pipelines on the circuit board through the
comparator.
Acquisition. Each acquisition circuit is made up of a single acquisition IC. Each
acquisition IC is a 34-channel state/timing logic analyzer. Two acquisition ICs are
included on every logic analyzer card for a total of 64 data channels and 4 clock/
data channels. All of the sequencing, storage qualification, pattern/range
recognition and event counting functions are performed by the acquisition IC.
Also, the acquisition ICs perform master clocking functions. All four state
acquisition clocks are sent to each acquisition IC, and the acquisition ICs
generate their own sample clocks. Every time the user selects RUN, the
acquisition ICs individually perform a clock optimization before data is stored.
Clock optimization involves using programmable delays in the acquisition ICs to
position the master clock transition where valid data is captured. This procedure
greatly reduces the effects of channel-to-channel skew and other propagation
delays.
In the timing acquisition mode, an oscillator-driven clock circuit provides a four-
phase 125-MHz clock signal to each of the acquisition ICs. For high speed timing
acquisition (125-MHz and faster), the four-phase 125-MHz clock signal
determines the sample period. For slower sample rates, one of the two
acquisition ICs divides the 125-MHz clock signal to the appropriate sample rate.
The sample clock is then sent to the other acquisition ICs.
Acquisition RAM. The acquisition RAM is external to the acquisition IC. The
acquisition RAM consists of 18 RAM ICs (256K x 16). A memory management