Service Guide Publication number 16740-97000 December 2001 For Safety information, Warranties, and Regulatory information, see the pages at the end of the book. © Copyright Agilent Technologies 2001 All Rights Reserved.
The Agilent 16740/41/42A Logic Analyzer—At a Glance The Agilent Technologies 16740/41/42A are 400-MHz state/800-MHz timing logic analyzer modules for the Agilent Technologies 16700-series logic analysis system. The 16740/41/42A offer high performance measurement capability.
The 16740/41/42A uses operating system version A.02.50.00 or higher. Agilent Technologies 16700-series mainframes with serial number prefix lower than US4148 are factory-installed with older operating system versions. If your mainframe operating system is older than the required version, contact your Agilent Technologies Service Center for newer software before attempting the performance verification procedures in chapter 3.
In This Book This book is the service guide for the 16740/41/42A 200-MHz state/800-MHz timing logic analyzer modules. This service guide has eight chapters. Chapter 1 contains information about the module and includes accessories for the module, specifications and characteristics of the module, and a list of the equipment required for servicing the module. Chapter 2 tells how to prepare the module for use. Chapter 3 gives instructions on how to test the performance of the module.
Contents 1 General Information Accessories 10 Mainframe and Operating System 10 Specifications 11 Characteristics 12 Environmental Characteristics 12 Recommended Test Equipment 13 2 Preparing for Use Power Requirements 16 Operating Environment 16 Storage 16 To inspect the module 16 To prepare the mainframe 17 To configure a one-card module 18 To configure a multi-card module 20 To install the module 26 To turn on the system 28 To test the module 28 To clean the module 29 3 Testing Performance To Perform
Contents To Test the Single-clock, Single-edge, State Acquisition 48 Set up the equipment 48 Set up the logic analyzer 48 Connect the logic analyzer 53 Verify the test signal 56 Check the setup/hold combination 58 To Test the Multiple-clock, Multiple-edge, State Acquisition Set up the equipment 66 Set up the logic analyzer 67 Connect the logic analyzer 71 Verify the test signal 74 Check the setup/hold with single clock edges, multiple clocks 76 To Test the Single-clock, Multiple-edge, State Acquisitio
Contents 5 Troubleshooting To use the flowcharts 128 To run the self-tests 131 To exit the test system 132 To test the cables 133 To test the auxiliary power 138 6 Replacing Assemblies Tools Required 140 To remove the module 140 To replace the circuit board 142 To replace the module 143 To replace the probe cable 144 To return assemblies 145 7 Replaceable Parts Replaceable Parts Ordering 148 Replaceable Parts List 149 Exploded View 151 8 Theory of Operation Block-Level Theory 154 Self-Tests Description
Contents 8
1 General Information This chapter lists the accessories, the specifications and characteristics, and the recommended test equipment.
Chapter 1: General Information Accessories The following accessories are supplied with the 16740/41/42A logic analyzer.
Chapter 1: General Information Specifications The specifications are the performance standards against which the product is tested.
Chapter 1: General Information Characteristics The characteristics are not specifications, but are included as additional information.
Chapter 1: General Information Recommended Test Equipment Equipment Required 5HFRPPHQGHG +3 $JLOHQW 0RGHO 3DUW 8VH 0+] QV SXOVH ZLGWK SV ULVH WLPH $ 2SWLRQ 3 7 'LJLWL]LQJ 2VFLOORVFRSH ≥ *+] EDQGZLGWK SV ULVH WLPH $ PDLQIUDPH ZLWK $ SOXJ LQ PRGXOH 3 )XQFWLRQ *HQHUDWRU $FFXUDF\ ≤ × IUHTXHQF\ '& RIIVHW YROWDJH 9 % 2SWLRQ 3 'LJLWDO 0XOWLPHWHU P9 UHVROXWLRQ DFFXUDF\ $ 3 %1& %DQDQD &DEOH
Chapter 1: General Information 14
2 Preparing for Use This chapter gives you instructions for preparing the logic analyzer module for use.
Chapter 2: Preparing for Use Power Requirements All power supplies required for operating the logic analyzer are supplied through the backplane connector in the mainframe. Operating Environment The operating environment is listed in chapter 1. Note the non-condensing humidity limitation. Condensation within the instrument can cause poor operation or malfunction. Provide protection against internal condensation.
Chapter 2: Preparing for Use mechanical defects. If you find any defects, contact your nearest Agilent Technologies Sales Office. Arrangements for repair or replacement are made, at Agilent Technologies’ option, without waiting for a claim settlement. To prepare the mainframe CAUTION: Turn off the mainframe power before removing, replacing, or installing the module. CAUTION: Electrostatic discharge can damage electronic components.
Chapter 2: Preparing for Use 4 Starting from the top, pull the cards and filler panels that need to be moved halfway out. CAUTION: All multi-card modules will be cabled together. Pull these cards out together. 5 Remove the cards and filler panels. Remove the cards or filler panels that are in the slots intended for the module installation. Push all other cards into the card cage, but not completely in. This is to get them out of the way for installing the module.
Chapter 2: Preparing for Use 19
Chapter 2: Preparing for Use To configure a multi-card module 1 Plan the configuration. Multicard modules can only be connected as shown in the illustration. Select the card that will be the master card, and set the remaining cards aside. 2 Obtain two 2x40 cables from the accessory pouch for every expander card being configured. One Expander: Two 2x40 cables Two Expanders: Four 2x40 cables Three Expanders: Six 2x40 cables Four Expanders: Eight 2x40 cables.
Chapter 2: Preparing for Use 3 Connect a 2x40 cable to J9 and to J10 of each card in the multicard configuration. 4 On the expander cards, disconnect the end of the 2x10 cable that is plugged into the connector labeled "Master." CAUTION: If you pull on the flexible ribbon part of the 2x10 cable, you might damage the cable assembly. Using your thumb and finger, grasp the ends of the cable connector.
Chapter 2: Preparing for Use 5 Begin stacking the cards together according to the drawing under step 1. While stacking, connect the free end of the 2x40 cable on the lower card J9 to J14 of the upper card, on the underside of the card.
Chapter 2: Preparing for Use 6 Feed the free end of the 2x10 cables of the lower expander cards through the access holes to the master card. Plug the 2x10 cables into J4 (bottommost expander in a five-card configuration) and J5 (expander that is next to the master card) on the master card.
Chapter 2: Preparing for Use 7 Stack the remaining expander boards on top of the master board. While stacking, connect the free end of the 2x40 cables on the lower card J10 and J9 to the upper card J15 and J14.
Chapter 2: Preparing for Use 8 Feed the free end of the 2x10 cables of the expander cards through the access holes to the master card. Plug the 2x10 cables into J7 (expander that is next to the master card) and J8 (top-most expander in a four- or five-card configuration) on the master card.
Chapter 2: Preparing for Use To install the module 1 Slide the cards above the slots for the module about halfway out of the mainframe. 2 With the probe cables facing away from the instrument, slide the module approximately halfway into the mainframe. 3 Slide the complete module into the mainframe, but not completely in. Each card in the instrument is firmly seated and tightened one at a time in step 5. 4 Position all cards and filler panels so that the endplates overlap.
Chapter 2: Preparing for Use 5 Seat the cards and tighten the thumbscrews. Starting with the bottom card, firmly seat the cards into the backplane connector of the mainframe. Keep applying pressure to the center of the card endplate while tightening the thumbscrews finger-tight. Repeat this for all cards and filler panels starting at the bottom and moving to the top. CAUTION: Correct air circulation keeps the instrument from overheating.
Chapter 2: Preparing for Use To turn on the system 1 Connect the power cable to the mainframe. 2 Turn on the instrument power switch. When you turn on the instrument power switch, the instrument performs powerup tests that check mainframe circuitry. After the powerup tests are complete, the screen will look similar to the sample screen below. To test the module The logic analyzer module does not require an operational accuracy calibration or adjustment.
Chapter 2: Preparing for Use To clean the module • With the mainframe turned off and unplugged, use mild detergent and water to clean the rear panel. • Do not attempt to clean the module circuit board.
Chapter 2: Preparing for Use 30
3 Testing Performance This chapter tells you how to test the performance of the logic analyzer against the specifications listed in chapter 1.
Chapter 3: Testing Performance To ensure the logic analyzer is operating as specified, software tests (self-tests) and manual performance tests are done. The logic analyzer is considered performance-verified if all of the software tests and manual performance tests have passed. The procedures in this chapter indicate what constitutes a “Pass” status for each of the tests. Test Strategy This chapter shows the module being tested in an Agilent Technologies 16700Bseries mainframe.
Chapter 3: Testing Performance To Perform the Self-tests To Perform the Self-tests There are two types of self-tests: self-tests that automatically run at power-up, and self-tests that you select on the screen. The self-tests verify the correct operation of the logic analysis system. Self-tests can be performed all at once or one at a time. While testing the performance of the logic analysis system, run the self-tests all at once.
Chapter 3: Testing Performance To Perform the Self-tests Perform the self-tests The self-tests verify the correct operation of the logic analysis system and the installed 16740/41/42A module. Self-tests can be performed all at once or one at a time. While testing the performance of the logic analysis system, run the self-tests all at once. 1 Launch the Self-Tests. a In the System window, click on System Admin. b Under the Admin tab, click on Self-Test. . .
Chapter 3: Testing Performance To Set Up the Test Connectors To Set Up the Test Connectors The test connectors connect the logic analysis system to the test equipment. Materials Required 'HVFULSWLRQ 5HFRPPHQGHG +3 $JLOHQW 3DUW 4W\ %1& I &RQQHFWRU Ω UHVLVWRU %HUJ 6WULS E\ %HUJ 6WULS E\ 3UREH $ -XPSHU ZLUH 1 Build three test connectors using BNC connectors and 6-by-2 sections of Berg strip.
Chapter 3: Testing Performance To Set Up the Test Connectors e Solder the ground tab of the BNC connector to the center pin of the other row on the Berg strip. f On two of the test connectors, solder a 20:1 probe. The probe ground goes to the same row of pins on the test connector as the BNC ground tab.
Chapter 3: Testing Performance To Set Up the Test Connectors 2 Build one test connector using a BNC connector and a 17-by-2 section of Berg strip. a Solder a jumper wire to all pins on one side of the Berg strip. b Solder a jumper wire to all pins on the other side of the Berg strip. c Solder the center of the BNC connector to the center pin of one row on the Berg strip. d Solder the ground tab of the BNC connector to the center pin of the other row on the Berg strip.
Chapter 3: Testing Performance To Set up the Test Equipment and the Analyzer To Set up the Test Equipment and the Analyzer Before testing the specifications of the 16740/41/42A logic analyzer, the test equipment and the logic analysis system must be set up and configured. These instructions include detailed steps for initially setting up the required test equipment and the logic analysis system. Before performing any or all of the following tests in this chapter, the following steps must be followed.
Chapter 3: Testing Performance To Set up the Test Equipment and the Analyzer d In the Analyzer Setup window, select the Sampling tab. 4 Set up the pulse generator according to the following table.
Chapter 3: Testing Performance To Test the Threshold Accuracy To Test the Threshold Accuracy Testing the threshold accuracy verifies the performance of the following specification: • Clock and data channel threshold accuracy These instructions include detailed steps for testing the threshold settings of Pod 1. After testing Pod 1, connect and test the rest of the pods one at a time. To test the next pod, follow the detailed steps for Pod 1, substituting the next pod for Pod 1 in the instructions.
Chapter 3: Testing Performance To Test the Threshold Accuracy Set up the logic analyzer 1 In the Analyzer Setup window, select the Format tab. 2 Under the Format tab, select Pod Assignment. Unassign the pods that are assigned to Analyzer 2. To unassign the pods, use the mouse to drag the pods to the Unassigned Pods column. Select Close to close the Pod Assignment Window. 3 Under the Format tab, select the Threshold field under Pod 1.
Chapter 3: Testing Performance To Test the Threshold Accuracy Connect the logic analyzer 1 Using the 17-by-2 test connector, BNC cable, and probe tip assembly, connect the data and clock channels of Pod 1 to one side of the BNC Tee. 2 Using a BNC-banana cable, connect the voltmeter to the other side of the BNC Tee. 3 Connect the BNC Tee to the Main Signal output of the function generator.
Chapter 3: Testing Performance To Test the Threshold Accuracy Test the ECL threshold 1 In the Pod Threshold window, select the Standard threshold voltage field. At the pop-up menu select ECL (–1.30 V). 2 On the function generator front panel, enter -1.214 V ±1 mV DC offset. Use the multimeter to verify the voltage. The activity indicators for Pod 1 should show all data channels and the J-clock channel at a logic high.
Chapter 3: Testing Performance To Test the Threshold Accuracy 3 Using the Modify down arrow on the function generator, decrease offset voltage in 1-mV increments until all activity indicators for the pod under test show the channels are at a logic low. Record the function generator voltage in the performance test record.
Chapter 3: Testing Performance To Test the Threshold Accuracy 4 Using the Modify up arrow on the function generator, increase offset voltage in 1-mV increments until all activity indicators for the pod under test show the channels are at a logic high. Record the function generator voltage in the performance test record.
Chapter 3: Testing Performance To Test the Threshold Accuracy Test the 0 V User threshold 1 In the Pod Threshold window, select User Defined. In the numeric field, enter 0 V. 2 On the function generator front panel, enter +0.067 V ±1 mV DC offset. Use the multimeter to verify the voltage. The activity indicators for the pod under test should show all data channels and the J-clock channel at a logic high.
Chapter 3: Testing Performance To Test the Threshold Accuracy 4 Using the Modify up arrow on the function generator, increase offset voltage in 1-mV increments until all activity indicators for the pod under test show the channels at a logic high. Record the function generator voltage in the performance test record.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition To Test the Single-clock, Single-edge, State Acquisition Testing the single-clock, single-edge, state acquisition verifies the performance of the following specifications: • Minimum master to master clock time • Maximum state acquisition speed • Setup/Hold time This test checks a combination of data channels using a single-edge clock at two selected setup/hold times.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 2 Assign all pods to Analyzer 1. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select Pod Assignment. c In the Pod Assignment window, use the mouse to drag the pods to the Analyzer 1 column. d Select Close to close the Pod Assignment window.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 3 Set up the Format tab. a Under one of the pod fields, select TTL. b In the Pod Threshold window, ensure the Apply threshold setting to all pods checkbox is checked. c In the Pod Threshold window, select the Standard threshold voltage field. At the pop-up menu, select ECL (–1.30 V). d Select Close to close the Pod Threshold window.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 4 Set up the Trigger tab. a In the Analyzer setup window, select the Trigger tab. Under the Trigger tab, select the Settings tab. b Select the Acquisition Depth field, then select “8K”. c Select the Trigger Position field, then select Start.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 5 Set up the Listing window. a In the Listing window, select the Markers tab. b Select the G1: field and the Markers Setup window appears. c Select the Time field associated with G1, and select Pattern. Select the Time field associated with G2, and select Pattern. Note: Leave the Marker Setup window open. You will be entering numeric values in the “occurs” field after acquiring the test data.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition Connect the logic analyzer 1 Using the 6-by-2 test connectors, connect the logic analyzer clock and data channels listed in the following tables to the pulse generator. 2 Using SMA cables, connect channel 1, channel 2, and trigger from the oscilloscope to the pulse generator according to the following illustration.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 3 Activate the data channels that are connected according to the previous table. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select the field showing the channel assignments for one of the pods being tested, then select Individual. Using the mouse, select the data channels to be tested (channels 11 and 3 of each pod). An asterisk means that a channel is turned on.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 4 Configure the trigger pattern. a Select the Trigger tab. Under the Trigger tab, select the Trigger Functions tab. b In the General State field, select Store nothing until pattern occurs. Then select Replace. c Under Trigger Sequence, locate the Label 1 = trigger pattern field. Enter “AA” in the trigger pattern field.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition Verify the test signal 1 Check the clock period. Using the oscilloscope, verify that the master-tomaster clock time is 5.000 ns, +0 ps or -100 ps. a Turn on the pulse generator channel 1, channel 2, and trigger outputs. b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the clock waveform so that a rising edge appears at the left of the display.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 2 Check the data pulse width. Using the oscilloscope, verify that the data pulse width is 2.500 ns, +0 ps or -50 ps. a In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the data waveform so that the waveform is centered on the screen. b On the oscilloscope, select [Shift] + width: channel 1, then select [Enter] to display the data signal pulse width (+ width(1)).
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition Check the setup/hold combination 1 Select the logic analyzer setup/hold time. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select Setup/Hold. c In the Setup and Hold window, ensure All bits is selected. d Enter the setup time of the setup/hold combination to be tested in the Setup: field.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 3 Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup/hold combination selected, +0.0 ps or -50 ps. a On the Oscilloscope, select [Define meas] Define ∆Time - Stop edge: rising. b In the oscilloscope timebase menu, select Position.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 4 Select the clock to be tested. a In the Analyzer setup window, select the Sampling tab. b Under the Sampling tab, select the clock edge field under the clock to be tested. Then select Rising Edge. Turn off all other clocks. The first time through this test, select the first clock and edge. Clocks - ↑ .↑ /↑ 0↑ c Connect the clock input channel to be tested to the pulse generator channel 1 OUTPUT.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 5 Verify the test data. a In the Listing window, select Run. The display should show an alternating pattern of “AA” and “55”. b In the Marker Setup window, select the Define... field associated with G1, and the G1 Marker Pattern window appears. In the pattern field, enter “AA”. Select Apply, then select Close. If the label selection field reads Label1_TZ, you must select Label1 for the search term.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition If the Label selection field reads Label1_TZ, you must select Label1 for the search term. Follow the same procedure as in b above. d In the Marker Setup window, select the ‘occurs’ value field that corresponds to marker G1. Enter 4095. e In the Marker Setup window, select the ‘occurs’ value field that corresponds to marker G2. Enter 4096. f Select Close to apply the marker values to the data.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 8 Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup/hold combination selected, +0.0 ps or -50 ps. a On the Oscilloscope, select [Define meas] Define ∆Time - Stop edge: falling. b On the oscilloscope, select [Shift] ∆Time. Select Start src: channel 1, then select [Enter] to display the setup time (∆Time(1)-(2)).
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 9 Select the clock to be tested. a In the Analyzer setup window, select the Sampling tab. b Under the Sampling tab, select the clock edge field under the clock to be tested. Then select Falling Edge. The first time through this test, select the first clock and edge. Ensure all other clocks are turned off. Clocks -↓ .↓ /↓ 0↓ c Connect the clock input channel to be tested to the pulse generator channel 1 OUTPUT.
Chapter 3: Testing Performance To Test the Single-clock, Single-edge, State Acquisition 12 If the setup/hold used for the previous steps was 4.5/-2.0 ns, repeat steps 1 through 11 using setup/hold -2.0/4.5 ns. If the setup/hold used for the previous steps was -2.0/4.5 ns, continue on with the next section.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition To Test the Multiple-clock, Multiple-edge, State Acquisition Testing the multiple-clock, multiple-edge, state acquisition verifies the performance of the following specifications: • Minimum master to master clock time • Maximum state acquisition speed • Setup/Hold time This test checks a combination of data channels using multiple clocks at two selected setup/hold times.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition Set up the logic analyzer Perform the following steps if you have not already done so for the previous test. 1 Set up the Sampling tab. a In the Analyzer setup window, select the Sampling tab. b Select State Mode. 2 Assign all pods to Analyzer 1. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select Pod Assignment.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 3 Set up the Format tab. a Under one of the pod fields, select TTL. b In the Pod Threshold window, ensure the Apply threshold setting to all pods checkbox is checked. c In the Pod Threshold window, select the Standard threshold voltage field. At the pop-up menu, select ECL (–1.30V). d Select Close to close the Pod Threshold window.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 4 Set up the Trigger tab. a In the Analyzer setup window, select the Trigger tab. Under the Trigger tab, select the Settings tab. b Select the Acquisition Depth field, then select “8K”. c Select the Trigger Position field, then select Start.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 5 Set up the Listing window. a In the Listing window, select the Markers tab. b Select the G1: field and the Markers Setup window appears. c Select the Time field associated with G1, and select Pattern. Select the Time field associated with G2, and select Pattern. Note: Leave the Marker Setup window open. You will be entering numeric values in the “occurs” field after acquiring the test data.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition Connect the logic analyzer 1 Using the 6-by-2 test connectors, connect the logic analyzer clock and data channels listed in the following table to the pulse generator. 2 Using SMA cables, connect channel 1, channel 2, and trigger from the oscilloscope to the pulse generator according to the following illustration.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 3 Activate the data channels that are connected according to the previous table. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select the field showing the channel assignments for one of the pods being tested, then select Individual. Using the mouse, select the data channels to be tested (channels 11 and 3 of each pod). An asterisk means that a channel is turned on.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 4 Configure the trigger pattern. a Select the Trigger tab. Under the Trigger tab, select the Trigger Functions tab. b In the General State field, select Store nothing until pattern occurs. Then select Replace. c Under Trigger Sequence, locate the Label 1 = trigger pattern field. Enter “AA” in the trigger pattern field.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition Verify the test signal 1 Check the clock period. Using the oscilloscope, verify that the master-tomaster clock time is 5.000 ns, +0 ps or -100 ps. a Turn on the pulse generator channel 1, channel 2, and trigger outputs. b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the clock waveform so that a rising edge appears at the left of the display.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 2 Check the data pulse width. Using the oscilloscope, verify that the data pulse width is 3.000 ns, +0 ps or - 50 ps. a In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the data waveform so that the waveform is centered on the screen. b On the oscilloscope, select [Shift] + width: channel 1, then select [Enter] to display the data signal pulse width (+ width (1)).
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition Check the setup/hold with single clock edges, multiple clocks 1 Select the logic analyzer setup/hold time. a In the Analyzer setup window, select the Sampling tab. b Under the Sampling tab, select and activate any two clock edges. You must have two single-edge clocks selected before the Setup/Hold window will allow a Setup/Hold of 5.0/-2.0 ns. c Select the Format tab. Under the Format tab, select Setup/Hold.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 3 Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup/hold combination selected, +0.0 ps or -50 ps. a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising. b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob, position the rising edge of the clock waveform so that it is centered on the display.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 4 Select the clock combination to be tested. a In the Analyzer setup window, select the Sampling tab. b Under the Sampling tab, select the clock edge field under each clock. Then select Rising Edge. The clock setup field should show J↑ + K↑ + L↑ + M↑.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 5 Verify the test data. a In the Listing window, select Run. The display should show an alternating pattern of “AA” and “55”. b In the Marker Setup window, select the Define... field associated with G1, and the G1 Marker Pattern window appears. In the pattern field, enter “AA”. Select Apply, then select Close. If the label selection field reads Label1_TZ, you must select Label1 for the search term.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition If the Label selection field reads Label1_TZ, you must select Label1 for the search term. Follow the same procedure as in b above. d In the Marker Setup window, select the ‘occurs’ value field that corresponds to marker G1. Enter 4095. e In the Marker Setup window, select the ‘occurs’ value field that corresponds to marker G2. Enter 4096. f Select Close to apply the marker values to the data.
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 8 Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup/hold combination selected, +0.0 ps or -50 ps. a On the Oscilloscope, select [Define meas] Define ∆Time - Stop edge: falling. b On the oscilloscope, select [Shift] ∆Time. Select Start src: channel 1, then select [Enter] to display the setup time (∆Time(1)-(2)).
Chapter 3: Testing Performance To Test the Multiple-clock, Multiple-edge, State Acquisition 9 Select the clock combination to be tested. a In the Analyzer setup window, select the Sampling tab. b Under the Sampling tab, select the clock edge field under each clock. Then select Falling Edge. The clock setup field should show J↓ + K↓ + L↓ + M↓. 10 Verify the test data. a In the Listing window, select Run. The display should show an alternating pattern of “AA” and “55”.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition To Test the Single-clock, Multiple-edge, State Acquisition Testing the single-clock, multiple-edge, state acquisition verifies the performance of the following specifications: • Minimum master to master clock time • Maximum state acquisition speed • Setup/Hold time This test checks a combination of data channels using a multiple-edge single clock at two selected setup/hold times.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition Set up the logic analyzer Perform the following steps if you have not done so for the previous tests. 1 Set up the Sampling tab. a In the Analyzer window, select the Sampling tab. b Select State Mode. 2 Assign all pods to Analyzer 1. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select Pod Assignment.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition 3 Set up the Format tab. a Under one of the pod fields, select TTL. b In the Pod Threshold window, ensure the Apply threshold setting to all pods checkbox is checked. c In the Pod Threshold window, select the Standard threshold voltage field. At the pop-up menu, select ECL (–1.30 V). d Select Close to close the Pod Threshold window.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition 4 Set up the Trigger tab. a In the Analyzer setup window, select the Trigger tab. Under the Trigger tab, select the Settings tab at the bottom of the window. b Select the Acquisition Depth field, then select “8K”. c Select the Trigger Position field, then select Start.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition 5 Set up the Listing window. a In the Listing window, select the Markers tab. b Select the G1: field and the Markers Setup window appears. c Select the Sample field associated with G1, and select Pattern. Select the Sample field associated with G2, and select Pattern. Note: Leave the Marker Setup window open. You will be entering numeric values in the “occurs” field after acquiring the test data.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition Connect the logic analyzer 1 Using the 6-by-2 test connectors, connect the logic analyzer clock and data channels listed in the following tables to the pulse generator. 2 Using SMA cables, connect channel 1, channel 2, and trigger from the oscilloscope to the pulse generator according to the following illustration.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition 3 Activate the data channels that are connected according to the previous table. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select the field showing the channel assignments for one of the pods being tested, then select Individual. Using the mouse, select the data channels to be tested (channels 11 and 3 of each pod). An asterisk means that a channel is turned on.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition 4 Configure the trigger pattern. a Select the Trigger tab. Under the Trigger tab, select the Trigger Functions tab. b In the General State field, select Store nothing until pattern occurs. Then select Replace. c Under Trigger Sequence, locate the Label 1 = trigger pattern field. Enter “AA” in the trigger pattern field.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition Verify the test signal 1 Check the clock interval. Using the oscilloscope, verify that the master-tomaster clock time is 5.000 ns, +0 ps or -100 ps. a Turn on the pulse generator channel 1, channel 2, and trigger outputs. b In the oscilloscope Timebase menu, select Scale: 2.000 ns/div. c In the oscilloscope Timebase menu, select Position.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition 2 Check the data pulse width. Using the oscilloscope, verify that the data pulse width is 3.000 ns, +0 ps or -50 ps. a In the oscilloscope Timebase menu, select Scale: 1.000 ns/div. b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the data waveform so that the waveform is centered on the screen.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition Check the setup/hold with single clock, multiple clock edges 1 Select the logic analyzer setup/hold time. a In the Analyzer setup window select the Sampling tab. b Under the Sampling tab, select and activate a rising and falling edge for any clock. The Setup/Hold window requires a double clock edge before it will allow a setup/hold of 5.0/-2.0 ns. c Select the Format tab. Under the Format tab, select Setup/Hold.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition 2 Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup/hold combination selected, +0.0 ps or -50 ps. a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising. b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob, position the falling edge of the data waveform so that it is centered on the display.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition 3 Select the clock to be tested. a In the Analyzer setup window, select the Sampling tab. b Under the Sampling tab, select the clock edge field under the clock to be tested. Then select Both Edges. Clocks -↕ .↕ /↕ 0↕ c Connect the clock input channel to be tested to the pulse generator channel 1 OUTPUT. Disconnect all other clock input channels.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition 4 Verify the test data. a In the Listing window, select Run. The display should show an alternating pattern of “AA” and “55”. b In the Marker Setup window, select the Define... field associated with G1, and the G1 Marker Pattern window appears. In the pattern field, enter “AA”. Select Apply, then select Close. If the label selection field reads Label1_TZ, you must select Label1 for the search term.
Chapter 3: Testing Performance To Test the Single-clock, Multiple-edge, State Acquisition If the Label selection field reads Label1_TZ, you must select Label1 for the search term. Follow the same procedure as in b above. d In the Marker Setup window, select the ‘occurs’ value field that corresponds to marker G1. Enter 4095. e In the Marker Setup window, select the ‘occurs’ value field that corresponds to marker G2. Enter 4096. f Select Close to apply the marker values to the data.
Chapter 3: Testing Performance To Test the Time Interval Accuracy To Test the Time Interval Accuracy Testing the time interval accuracy does not check a specification, but does check the following: • 125 MHz oscillator This test verifies that the 125-MHz timing acquisition synchronizing oscillator is operating within limits.
Chapter 3: Testing Performance To Test the Time Interval Accuracy 3 Set up the function generator according to the following table. Function Generator Setup )UHT 0+] $PSWG 9 0RGXODWLRQ 2II Set up the logic analyzer 1 Set up the Sampling tab. a In the Analyzer setup window, select the Sampling tab. b Select Timing Mode. c In Timing Mode Controls, select Trigger Position. Then select Start. d Select the Acquisition Depth field. Then select “512K”. e Select the sample period field.
Chapter 3: Testing Performance To Test the Time Interval Accuracy 2 Set up the Format tab. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select Pod Assignment. c In the Pod Assignment window, use the mouse to drag Pods 1 and 2 to the Analyzer 1 column. Use the mouse to drag pods 3 and 4 to the Unassigned column. d Select Close to close the Pod Assignment window. e Under the Format tab, select the field showing the channel assignments for Pod 1.
Chapter 3: Testing Performance To Test the Time Interval Accuracy g In the Pod Threshold window, select the Standard threshold voltage field. At the pop-up menu select ECL (–1.30 V). 3 Set up the Waveform window. a In the Analyzer setup window, select Window, then select Slot n: Analyzer (where “n” is the slot you have the module installed), then select Waveform. A Waveform window opens. b In the Waveform window select the Markers tab. c Select the G1 field and a Marker Setup window appears.
Chapter 3: Testing Performance To Test the Time Interval Accuracy Connect the logic analyzer 1 Using a 6-by-2 test connector, connect channel 0 of Pod 1 to the pulse generator channel 2 output. 2 Using the SMA cable and the BNC adapter, connect the External Input of the pulse generator to the Main Signal of the function generator. Acquire the data 1 Enable the pulse generator channel 2 and trigger outputs (with the LED off). 2 In the logic analyzer Waveform window, select Run.
Chapter 3: Testing Performance To Test the Time Interval Accuracy 3 Configure the Markers to measure the time interval. a In the Marker Setup window select the Time field associated with G1, and select Pattern. Select the Time field associated with G2, and select Pattern. b Select the Occurs field associated with G1 and enter “1”. Select the Occurs field associated with G2 and enter “30000”. c Select the From field associated with G2 and select G1.
Chapter 3: Testing Performance To Test the Time Interval Accuracy e In the marker Setup window, select the Define... field associated with G2, and the G2 Marker Pattern window appears. In the Pattern field, enter “1”. Select the Pattern Qualify field and select When Entering. If the Label selection field reads Label1_TZ, you must select Label1 for the search term. Follow the same procedure as in b above. In the Marker Pattern window, select Apply, then select Close. 4 Acquire the data.
Chapter 3: Testing Performance To Test the Multi-Card Module To Test the Multi-Card Module The multi-card test is only required for configured multi-card modules. Performing the test verifies the performance of the following specifications: • Minimum master to master clock time • Maximum state acquisition speed • Setup/Hold time Multi-card modules that were changed to one-card modules for the previous performance tests need to be reconfigured as a multi-card module for this test.
Chapter 3: Testing Performance To Test the Multi-Card Module Set up the logic analyzer 1 Set up the Sampling tab. a In the Analyzer setup window, select the Sampling tab. b Select State Mode. 2 Assign pods 1 and 2 of the master card and all expander cards to Analyzer 1. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select Pod Assignment. c In the pod Assignment window, use the mouse to drag the pods 1 and 2 to the Analyzer 1 column.
Chapter 3: Testing Performance To Test the Multi-Card Module 3 Set up the Format tab. a Under one of the pod fields, select TTL. b In the Pod Threshold window, ensure the Apply threshold settings to all pods checkbox is checked. c In the Pod Threshold window, select the Standard threshold voltage field. At the pop-up menu select ECL (–1.30 V). d Select Close to close the Pod Threshold window.
Chapter 3: Testing Performance To Test the Multi-Card Module 4 Set up the Trigger tab. a In the Analyzer setup window, select the Trigger tab. Under the Trigger tab, select the Settings tab. b Select the Acquisition Depth field, then select “8K”. c Select the Trigger Position field, then select Start.
Chapter 3: Testing Performance To Test the Multi-Card Module 5 Set up the Listing window. a In the Listing window, select the Markers tab. b Select the G1: field and the Markers Setup window appears. c Select the Time field associated with G1, and select Pattern. Select the Time field associated with G2, and select Pattern. Note: Leave the Marker Setup window open. You will be entering numeric values in the “occurs” field after acquiring the test data.
Chapter 3: Testing Performance To Test the Multi-Card Module Connect the logic analyzer 1 Using the 6-by-2 test connectors, connect the logic analyzer clock and data channels listed in the following tables to the pulse generator. 2 Using SMA cables, connect channel 1, channel 2, and trigger from the oscilloscope to the pulse generator according to the following illustration.
Chapter 3: Testing Performance To Test the Multi-Card Module 3 Activate the data channels that are connected according to the previous table. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select the field showing the channel assignments for Pod 1 of one of the Expander cards, then select Individual. Using the mouse, select channels 3 and 11. An asterisk means that a channel is turned on.
Chapter 3: Testing Performance To Test the Multi-Card Module 4 Configure the trigger pattern a Select the Trigger tab. Under the Trigger tab, select the Trigger Functions tab. b In the General State field, select Store nothing until pattern occurs. Then select Replace. c Under Trigger Sequence, locate the Label 1 = trigger pattern field. Enter the pattern according to the following table.
Chapter 3: Testing Performance To Test the Multi-Card Module Verify the test signal 1 Check the clock period. Using the oscilloscope, verify that the master-tomaster clock time is 5.000 ns, +0 ps or -100 ps. a Turn on the pulse generator channel 1, channel 2, and trigger outputs. b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the clock waveform so that a rising edge appears at the left of the display.
Chapter 3: Testing Performance To Test the Multi-Card Module 2 Check the data pulse width. Using the oscilloscope, verify that the data pulse width is 2.500 ns, +0 ps or -50 ps. a In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the data waveform so that the waveform is centered on the screen. b On the oscilloscope, select [Shift] + width: channel 1, then select [Enter] to display the data signal pulse width (+ width(1)).
Chapter 3: Testing Performance To Test the Multi-Card Module Check the setup/hold combination 1 Select the logic analyzer setup/hold time. a In the Analyzer setup window, select the Format tab. b Under the Format tab, select Setup/Hold. c In the Setup and Hold window, ensure All bits is selected. d Enter 4.500 ns in the Setup: field. e Select the close (X) button in the upper-right corner to close the Setup/ Hold window. 2 Disable the pulse generator channel 1 COMP (LED off).
Chapter 3: Testing Performance To Test the Multi-Card Module 3 Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup/hold combination selected, +0.0 ps or -50 ps. a On the Oscilloscope, select [Define meas] Define ∆Time - Stop edge: rising. b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob, position both a clock and a data waveform on the display, with the rising edge of the clock waveform centered on the display.
Chapter 3: Testing Performance To Test the Multi-Card Module 4 Select the clock to be tested. a In the Analyzer setup window select the Sampling tab. b Under the Sampling tab, select the clock edge field under the clock to be tested. Then select Rising Edge. Clocks - ↑ .↑ /↑ 0↑ c Connect the clock input channel to be tested to the pulse generator channel 1 OUTPUT. Disconnect all other clock input channels.
Chapter 3: Testing Performance To Test the Multi-Card Module 5 Verify the test data. a In the Listing window, select Run. The display should show an alternating pattern of “A” and “5” (2-card module) “2A” and “15” (3-card module) “AA” and “55” (4- or 5-card module).
Chapter 3: Testing Performance To Test the Multi-Card Module b In the Marker Setup window, select the Define... field associated with G1, and the G1 Marker Pattern window appears. In the pattern field, enter “A” (2-card module) “2A” (3-card module) or “AA” (4- or 5-card module). Select Apply, then select Close. If the label selection field reads Label1_TZ, you must select Label1 for the search term. To do this, select Label1_TZ; then, in the popup menu, select Replace label.
Chapter 3: Testing Performance To Test the Multi-Card Module e In the Marker Setup window, select the ‘occurs’ value field that corresponds to marker G2. Enter 4096. f Select Close to apply the marker values to the data. If the “Pattern NOT found for marker…” error message does not appear, then the test passes. Record the Pass or Fail in the performance test record. 6 Repeat steps 4 and 5 for the next clock edge listed in the table in step 4, until all listed clock edges have been tested.
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Chapter 3: Testing Performance Performance Test Record 124
4 Calibrating This chapter gives you instructions for calibrating the logic analyzer.
Chapter 4: Calibrating Calibration Strategy The 16740/41/42A logic analyzer does not require an operational accuracy calibration. To test the module against the module specifications, refer to "Testing Performance" in chapter 3.
5 Troubleshooting This chapter helps you troubleshoot the module to find defective assemblies.
Chapter 5: Troubleshooting The troubleshooting consists of flowcharts, self-test instructions, a cable test, and a test for the auxiliary power supplied by the probe cable. If you suspect a problem, start at the top of the first flowchart. During the troubleshooting instructions, the flowcharts will direct you to perform the selftests or the cable test. The service strategy for this instrument is the replacement of defective assemblies.
Chapter 5: Troubleshooting Troubleshooting Flowchart 1 129
Chapter 5: Troubleshooting Troubleshooting Flowchart 2 130
Chapter 5: Troubleshooting To run the self-tests Self-tests identify the correct operation of major, functional subsystems of the module. You can run all self-tests without accessing the module. If a self-test fails, the troubleshooting flowcharts instruct you to change a part of the module. To run the self-tests: 1 In the System window, select System Admin. 2 In the System Administration window, select the Admin tab, then select Self-Test. At the Test Query window, select Yes.
Chapter 5: Troubleshooting Refer to Chapter 8 in the mainframe service manual for more information on system tests that are not executed. To exit the test system To exit the test system 1 Select Close to close any module or system test windows. 2 In the Self Test window, select Quit. 3 In the session manager window, select Start Session to launch a new logic analyzer session.
Chapter 5: Troubleshooting To test the cables This test allows you to functionally verify the probe cable and probe tip assembly of any of the logic analyzer pods. Only one probe cable can be tested at a time. Repeat this test for each probe cable to be tested.
Chapter 5: Troubleshooting 3 Set up the Sampling tab. a In the Analyzer setup window, select the Sampling tab. b Select State Mode. c Select Master Clock. In the Master Clock window, select both edges for the J clock (J↕). Turn off the other clocks. d Select Acquisition Depth field, then select 8K.
Chapter 5: Troubleshooting 4 Assign all pods to Analyzer 1, and configure the pod under test. a Select the Format tab. Under the Format tab, select Pod Assignment. b Use the mouse to drag the pods to the Analyzer 1 column. c Select the field showing the channel assignments for the pod under test. In the pop-up menu, select the asterisk field to put asterisks in the channel positions, activating the channels. Select Done. d Select Setup/Hold, then enter 3.000 ns in the Setup: field.
Chapter 5: Troubleshooting 5 Set up the Listing window. a In the Analyzer Setup window, select Window, then select Slot n: Analyzer (where “n” is the slot the module under test is installed), then select Listing. A Listing window opens. b Right click on the Hex field and change the Lab1 base to Binary. 6 Using four 6-by-2 test connectors, connect the logic analyzer to the pulse generator channel outputs. To make the test connectors, see chapter 3, "Testing Performance.
Chapter 5: Troubleshooting 7 On the logic analyzer, select Run. The listing should look similar to the figure below. Ignore any error messages dealing with the G1 and G2 markers. 8 If the listing looks like the figure, then the cable passed the test. If the listing does not look similar to the figure, then there is a possible problem with the cable or probe tip assembly. Causes for cable test failures include: • open channel. • channel shorted to a neighboring channel.
To test the auxiliary power The +5 V auxiliary power is protected by a current overload protection circuit. If the current on pins 1 and 39 exceeds 0.33 amps, the circuit will open. When the short is removed, the circuit will reset in approximately 1 minute. There should be +5 V after the 1 minute reset time.
6 Replacing Assemblies This chapter contains the instructions for removing and replacing the logic analyzer module, the circuit board of the module, and the probe cables of the module as well as the instructions for returning assemblies.
Chapter 6: Replacing Assemblies CAUTION: Turn off the instrument before installing, removing, or replacing a module in the instrument. Tools Required • A T10 TORX screwdriver, to remove screws connecting the probe cables and screws connecting the back panel. To remove the module CAUTION: Electrostatic discharge can damage electronic components. Use grounded wriststraps and mats when performing any service to this module. 1 Remove power from the instrument. a Exit all logic analysis sessions.
Chapter 6: Replacing Assemblies 5 Push all other cards into the card cage, but not completely in. This is to get them out of the way for removing and replacing the module. 6 If the module consist of a single card, replace the faulty card. If the module consists of multiple cards, remove the cables from J9 and J10 of all cards. Remove the 2x10 cables from J4, J5, J7, and J8 from the master card. Remove the faulty card from the module.
Chapter 6: Replacing Assemblies To replace the circuit board 1 Remove the three screws connecting the probe cables to the back panel, then disconnect the probe cables. 2 Remove the four screws attaching the ground spring and back panel to the circuit board, then remove the back panel and the ground spring. 3 Replace the faulty circuit board with a new circuit board. On the faulty board, make sure the 20-pin ribbon cable is connected between J3 and J6.
Chapter 6: Replacing Assemblies To replace the module 1 If the module consists of one card, go to step 2. If the module consists of more than one card, connect the cables together in a master/expander configuration. Follow the procedure "To configure a multicard module" in chapter 2. 2 Slide the cards above the slots for the module about halfway out of the mainframe. 3 With the probe cables facing away from the instrument, slide the module approximately halfway into the mainframe.
Chapter 6: Replacing Assemblies 5 Position all cards and filler panels so that the endplates overlap. 6 Seat the cards and tighten the thumbscrews. Starting with the bottom card, firmly seat the cards into the backplane connector of the mainframe. Keep applying pressure to the center of the card endplate while tightening the thumbscrews finger-tight. Repeat this for all cards and filler panels starting at the bottom and moving to the top.
Chapter 6: Replacing Assemblies ordering information. 5 Install the screws connecting the probe cable to the rear panel of the module. CAUTION: If you over tighten the screws, the threaded inserts on the back panel might break off of the back panel. Tighten the screws only enough to hold the cable in place. To return assemblies Before shipping the module to Agilent Technologies, contact your nearest Agilent Technologies Sales Office for additional details. In the U.S., call 1-800-403-0801.
Chapter 6: Replacing Assemblies You can use either the original shipping containers, or order materials from an Agilent Technologies sales office. CAUTION: For protection against electrostatic discharge, package the module in electrostatic material. 4 Seal the shipping container securely, and mark it FRAGILE.
7 Replaceable Parts This chapter contains information for identifying and ordering replaceable parts for your module.
Chapter 7: Replaceable Parts Replaceable Parts Ordering Parts listed To order a part on the list of replaceable parts, quote the Agilent Technologies part number, indicate the quantity desired, and address the order to the nearest Agilent Technologies Sales Office. Parts not listed To order a part not on the list of replaceable parts, include the model number and serial number of the module, a description of the part (including its function), and the number of parts required.
Chapter 7: Replaceable Parts Agilent Technologies Sales Office for information. See Also "To return assemblies," page 146. Replaceable Parts List The replaceable parts list is organized by reference designation and shows exchange assemblies, electrical assemblies, then other parts.
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Chapter 7: Replaceable Parts Exploded View Exploded view of the 16740/41/42A logic analyzer 151
8 Theory of Operation This chapter presents the theory of operation for the logic analyzer module and describes the self-tests.
Chapter 8: Theory of Operation The information in this chapter is to help you understand how the module operates and what the self-tests are testing. This information is not intended for component-level repair. Block-Level Theory The block-level theory of operation is divided into two parts: theory for the logic analyzer used as a single-card module or as a master card in a multi-card module, and theory for the logic analyzer used as an expander card in a multi-card module.
Chapter 8: Theory of Operation single ground. For applications where many channels are used (greater than three) and signal risetimes are less than 3 ns, individual channel grounds should be used. The probe tip networks comprise a series of resistors (250 Ohm) connected to a parallel combination of a 90 KOhm resistor and a 8.5 pF capacitor. The parallel 90 KOhm and 8.5 pF capacitor along with the lossy cable and terminations form a divide-by-ten probe system.
Chapter 8: Theory of Operation circuit controls RAM addressing during an acquisition run and during data upload to the mainframe CPU. Test and Clock Synchronization Circuit. ECLinPS (ECL in pico seconds) ICs are used in the Test and Clock Synchronization Circuit for reliability and low channel-to-channel skew. Test patterns are generated and sent to the comparators during software operation verification (self-tests).
Chapter 8: Theory of Operation The 16740/41/42A logic analyzer as an expander The logic analyzers can be connected together in multi-card master/expander configuration. All of the functions of the logic analyzer configured as a master are retained by the logic analyzer configured as an expander with a few exceptions.
Chapter 8: Theory of Operation Test and Clock Synchronization Circuit. The signals generated by the Test and Clock Synchronization Circuit of the master card are sent to all expander cards. Consequently, the Test and Clock Synchronization Circuit on each expander card is disabled to allow the master-configured card to drive the expander-configured card.
Chapter 8: Theory of Operation “1” and “0” is written to the first memory location. The contents of the first memory location is then downloaded and compared with known values. Passing the Memory Data Bus Test implies that data stored in the acquisition memory can be uploaded from the 16740/41/42A module to the 16700-series system. Memory Address Bus Test. The Memory Address Bus Test verifies the operation of the acquisition memory address bus.
Chapter 8: Theory of Operation Chip Registers Read/Write Test. The Chip Registers Read/Write Test verifies that the registers of each acquisition IC are operating properly. Test patterns are written to each register on each acquisition IC, read, and compared with known values. The registers are reset, and verified that each register has been initialized. Test patterns are then written to ensure the chip address lines are not shorted or opened.
Chapter 8: Theory of Operation that the procedure to test the Time Interval Accuracy in Chapter 3 provides a more reliable characterization of clock oscillator drift. Comparators Test. The Comparators Test ensures the data signal comparators in the module front end can be set to their maximum and minimum thresholds, and that they recognize activity at the signal inputs. A clock signal is routed to a test port on each comparator. The threshold is then set to the minimum value.
Chapter 8: Theory of Operation to see if self-calibration was successful. Passing the Calibration Test implies that the module can reliably perform an operation accuracy self-calibration every time Run is selected. Consequently the incoming data is optimized to reduce channel-to-channel skew so the acquisition ICs can reliably capture the incoming data. Zoom Data Lines Test. The Zoom Data Lines Test verifies the 2GHz TimingZoom controller data path.
Chapter 8: Theory of Operation Zoom Chip Select Test. The Zoom Chip Select Test verifies that each of the 2GHz TimingZoom memory ICs are individually selectable for data upload. Test data is acquired and stored in the TimingZoom FISO memory. The test data is then uploaded from each FISO memory IC and compared with known good data. Passing the Zoom Chip Select Test implies that each TimingZoom memory IC is individually addressable to upload TimingZoom data.
Chapter 8: Theory of Operation 164
Index Symbols +5 VDC supply, 156 Numerics 0 V user threshold, 46 A accessories, 10 acquisition, 155, 157 acquisition RAM, 155 analyzer connect, 42, 53, 71, 102, 110 set up, 41, 48, 67, 84, 88, 99, 106 assemblies exchange, 148 return, 145 B block-level theory, 154 C cable replace probe, 144 test, 133 calibrating see also testing performance calibration, 125–126 strategy, 126 test, 161 characteristics, 12 environmental, 12 chip registers, 161 circuit board replace, 142 clean module, 29 clock and data thresho
Index T test 0V user threshold, 46 analyzer chip memory bus, 160 analyzer memory bus SU/H measure, 160 cables, 133 calibration, 161 chip registers, 160 comparators, 161 connectors, 35 CPLD register, 158 ECL threshold, 43 equipment, 13, 32, 38 FPGA load, 158 FPGA register, 158 global and local arm lines, 161 HW assisted memory cell, 159 inter-chip resource bus, 161 inter-module flag bits, 161 interval, 32 master controller, 162 memory address bus, 159 memory data bus, 158 memory DMA unload, 159 memory sleep
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