Specifications

5-6. Silicon wafer C-V measurement
The C-V (capacitance vs. DC bias voltage) characteristic of a MOS structure is an important mea-
surement parameter for evaluating silicon wafers. To evaluate the capacitance that varies with
applied DC bias voltage, capacitance is measured at a low AC signal level while sweeping a number
of bias voltage points. Because the device usually exhibits a low capacitance (typically in the low
picofarads), the instrument must be able to measure low capacitance accurately with a high resolu-
tion at a low test signal level. Precise bias voltage output is also required for accurate C-V measure-
ment. Typical C-V measurement conditions are listed in Table 5-2. We recommend that you use an
auto balancing bridge instrument to achieve the required performance.
Figure 5-26 shows a measurement setup example using the 4294A precision impedance analyzer
with a prober. It is important that the Low terminal of the auto balancing bridge instrument not be
connected to the substrate, since the substrate is electrically connected to the prober’s noisy ground
and the Low terminal is sensitive to the noise. If the wafer chuck (stage) of the prober is isolated
from the ground and effectively guarded, the shielding conductor of the 4TP cable can be connected
to the prober’s guard terminal to minimize stray capacitance around the probes.
When a device with low resistivity is measured, applied DC voltage decreases due to DC leakage cur-
rent through the device, and this may cause C-V measurement error. Using the DC bias auto level
control (ALC) function helps to lessen this problem.
Table 5-2. Typical C-V measurement conditions
5-15
Frequency 10 kHz to 1 MHz
(10 kHz to 100 MHz for a thin gate oxide measurement)
Capacitance range 0.0001 pF to 1000 pF
Capacitance accuracy ± 0.1%
Test signal level 20 mVrms or 30 mVrms typical
DC bias voltage 0 V to ± 40 V
Bias voltage resolution ≤ 10 mV
Bias voltage accuracy ± 0.1%