Specifications

Specifications
Maximum State Speed 100 MHz (1660A through 1663A)
50 MHz (1664A)
Minimum State Clock Pulse Width
[2]
3.5 ns
Minimum Master to Master Clock Time
[2]
10.0 ns (1660A through 1663A)
20.0 ns (1664A)
Minimum Glitch Width 3.5 ns
Threshold Accuracy +/- (100 mV +3% of threshold setting)
Setup/Hold
[2]
one clock 3.5/0 ns to 0/3.5 ns
one edge (in 0.5 ns increments)
one clock 4.0/0 to 0/4.0 ns
both edges (in 0.5 ns increments)
multi clock 4.5/0 ns to 0/4.5 ns
multi edge (in 0.5 ns increments)
Specifications and Characteristics
Specifications
19–3