User`s guide

1-109
Making Measurements
Using Test Sequencing
Electrical specifications for TTL low:
• volts(L) ≤ 0.4 volts (V)
• current = 0.2 milliamps (mA)
Figure 1-78 Parallel Port Input and Output Bus Pin Locations in GPIO Mode
Test Set Interconnect Control
Figure 1-79 Test Set Interconnect Pin Designations
Control of the external switch (8762B Option T24) can be done through the test set
interface on the rear panel of the analyzer.
Pin 22 (TTL 1) on the TEST SET-I/O INTERCONNECT connector is a TTL line that
changes from TTL high to TTL low when changing TTL I/O FWD from 7 to 6. Refer to
Figure 1-79. To change from 7 to 6, press the following sequence:
• Press .
TTL I/O
TTL OUT
TESTSET I/O FWD
6 x1