Specifications

7
State (synchronous) analysis mode Option 250 Option 500
3
(Available on 16802A, 16803A, 16804A,
16806A, 16822A and 16823A)
tWidth*
1
1.5 ns 1.5 ns
tSetup 0.5 tWidth 0.5 tWidth
tHold 0.5 tWidth 0.5 tWidth
tSample range
2
–3.2 ns to +3.2 ns –3.2 ns to +3.2 ns
tSample adjustment resolution 80 ps typical 80 ps typical
Maximum state data rate on each channel 250 Mb/s 500 Mb/s
Memory depth
4
Option 001: 1 M samples Option 001: 1 M samples
Option 004: 4 M samples Option 004: 4 M samples
Option 016: 16 M samples Option 016: 16 M samples
Option 032: 32 M samples Option 032: 32 M samples
Number of independent analyzers
5
2 (1 for 16801A or 16821A) 1
Number of clocks
6
4 (2 for 16801A or 16821A) 1
Number of clock qualifiers
6
4 (2 for 16801A or 16821A) N/A
Minimum time between active clock edges *
, 7
4.0 ns 2.0 ns
Minimum master-to-slave clock time 1 ns N/A
Minimum slave-to-master clock time 1 ns N/A
Minimum slave-to-slave clock time 4.0 ns N/A
Minimum state clock pulse width
• Single edge
• Multiple edge
1.0 ns
1.0 ns
1.0 ns
2.0 ns
* Items marked with an asterisk (*) are specifications. All others are characteristics.
“Typical” represents the average or median value of the parameter based on measurements from a significant number of units.
1. Minimum eye width in system under test.
2. Sample positions are independently adjustable for each data channel input. A negative sample position causes the input to be syn-
chronously sampled by that amount before each active clock edge. A positive sample position causes the input to be synchronously
sampled by that amount after each active clock edge. A sampling position of zero causes the input to be synchronously sampled
coincident with each clock edge.
3. Use of eye finder is recommended in 450 MHz and 500 Mb/s state mode.
4. In 250 Mb/s state mode, with all pods assigned, memory depth is half the maximum memory depth. With one pod pair (34 channels)
unassigned, the memory depth is full. One pod pair (34 channels) must remain unassigned for time tags in 500 Mb/s state mode.
5. Independent analyzers may be either state or timing. When the 500 Mb/s state mode is selected, only one analyzer may be used.
6. In the 250 Mb/s state mode, the total number of clocks and qualifiers is 4 (2 for 16801A or 16821A).
7. Tested with input signal Vh = +1.3 V, Vl = +0.7 V, threshold = +1.0 V, tr/tf = 180 ps ± 30 ps (10%, 90%).
Clock Channel
Data EyevHeight
tWidth
vThreshold
tSetup tHold
tSample
Sampling Position
OV
Individual
Data Channe
l
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
(continued)