User's Manual

The module also has Rx and TX powerline filters.
RX and TX power line filters
Transistor Q301 is configured as a 5v power supply ripple filter. The filter reduces the
noise on the carrier and local oscillator signals.
VCO
The VCO comprises Q302, Coil L304, and varactor D301 D304 and is configured
as a Colpits oscillator. D301 D304 produces a change in frequency with a change in DC voltage
and is controlled by the tuning voltage signal present at the cathode. The local oscillator
programmable dividers. DATA is received by IC1 at pin 10 from pin 11of IC3.
The RF signal at the collector of Q302 is applied to an amplifier/buffer Q305.The amplified
Signal from Q305 passes to the prescaler ,IC1 pin8 .The RF signal at the collector of Q302 also
Drives the cascode amplifier/buffer formed by Q304 and Q305.
When D201 is forward biased (TX ON) , carrier frequencies at the collector of Q304 pass to the
Power amplifier and harmonic filter. When D303 is forward biased (RX ) , local oscillator
Frequencies at the collector of Q304 pass to the first mixer (Q102). VCQ1 adjusts the tuning
Voltage of the VCO to the correct operating point.
PLL IC
The reference frequency from the TCX O, at 12.8 MHZ , is connected to pin 1 of IC1(MB1504)
The appropriate VCO is connected to pin 11.
REFDIV divides the 12.8 MHz to produce a reference frequency (Fr) of 5 or 6. 25 kHz
dependent upon channel spacing selected. VARDIV divides the prescaled V CO frequency
to produce a variable frequency (Fv). Fv and Fr are fed to the phase detector.
Phase detector
When Fv=Fr, the phase detector output (pins 15 and 16,IC1) produces narrow negative pulses
And Fv and Fr pulse widths are identical. When Fv〉Fr pin 15 (V) pulses negative with pin 16
(R) remaining high. When Fv〈Fr pin 16 (R) pulses negative with pin 15(V) remaining high.
The signal at pin 15 and 16 is smoothed the loop filter and applied to the VCO.
Out-of-lock detector
The out-of-lock detector produces a series of logic level pulses when the loop is out of lock at
pin 7 of IC1.The pulses at pin 7 of IC1 are buffered by Q6 and then integrated by R17 and
C19. The product of the integrating circuit is fed to Base of Q201.
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