User manual

8
5.2.5 HOST Port Interface
Access to the 5
th
port of the HOST port of the UT200SpW4RTR can be accomplished by writing code targeted to the
Virtex 2 FPGA. Signals used to access the HOST port are listed below. Access to the HOST port can only be
achieved by using the V2. Be sure to jumper headers J6, J9, and J10 to ensure proper access from the PROM to the
V2 FPGA.
Table 1. UT200SpW4RTR Transmit HOST Port Connection Table
Virtex 2 – XC2V500 (FG256/FGG256) UT200WSpW4RTR – 255 LGA
Signal Description Pin Signal Name Pin
IO_L01P_0 B4 TXPORT0 C1
IO_L01N_0 C4 TXPORT1 D1
IO_L02P_0 C5 TXPORT2 F1
IO_L02N_0 D5 TXPORT3 G1
IO_L03P_0/VRN_0 A5 TXPORT4 C2
IO_L03N_0/VRP_0 B5 TXPORT5 D2
IO_L04P_0 C6 TXPORT6 E2
IO_L04N_0/VREF_0 D6 TXPORT7 F2
IO_L05P_0 A6 TXPORT8 G2
IO_L05N_0 B6 TX_PUSH D3
IO_L92P_0 E7 TX_FULL E3
IO_L92N_0 E6 TX_ALMOST_FULL F3
Table 2. UT200SpW4RTR Receive HOST Port Connection Table
Virtex 2 – XC2V500 (FG256/FGG256) UT200WSpW4RTR – 255 LGA
Signal Description Pin Signal Name Pin
IO_L01P_1 C13 RXPORT0 A3
IO_L01N_1 B13 RXPORT1 A4
IO_L02P_1 D12 RXPORT2 A6
IO_L02N_1 C12 RXPORT3 A7
IO_L03P_1/VRN_1 B12 RXPORT4 B3
IO_L03N_1/VRP_1 A12 RXPORT5 B4
IO_L04P_1/VREF_1 D11 RXPORT6 B5
IO_L04N_1 C11 RXPORT7 B6
IO_L05P_1 B11 RXPORT8 B7
IO_L05N_1 A11 RX_POP C4
IO_L92P_1 E11 RXEMPTY C5
IO_L92N_1 E10 RX_ALMOST_EMPTY C6
5.2.6 LEON-3FT HOST Port Access
The LEON-3FT evaluation board can also be used to control the FPGA and gain access to the HOST port of the
UT200SpW4RTR. The LEON-3FT device can access the UT200SpW4RTR by addressing the pins and signals listed
in the following table. This table shows the routing of the signal lines from the LEON-3FT to the Virtex 2 device.
The user can write code that will control the Virtex 2 such that the LEON has access to the HOST port of the SpW
router.