User manual

28
6.5.8 Look up table configuration Example 2
Assume the user wants to confirm the configuration write just preformed on look up table address 0x0020
was completed correctly. The user can then use the read configuration command. The following example
details hope to accomplish this.
• Address Bytes: 00, receive on port 5 (HOST port)
• 0x00 for configuration command
• Router ID: 00 is router ID (default)
• Protocol ID: 00 for no protocol used
• Packet Type: is Read No Clear 0x01
• Address LSB: 20
• Address MSB: 00 sets up to read from address 0x0020
• Count: 02 will read 2 Bytes of data. Count can only be an even number. To read one register you must enter
0x02, to read 2 registers you must enter 0x04, etc.
• Return Address Bytes: 01 05 out port 1 of Router A, out port 5 Router P
• Checksum: 28 this is the sum of the router ID, packet type, address bytes, count, an return address bytes.
0x00+0x00+0x00+0x01+0x20+0x00+0x02+0x05= 0x28
0 00 00 01 20 00 02 05 2
Protocol ID
Packet Type
Address LSB
Count
1 or More
Return Address
Bytes
Check Sum
100000000
EOP
0 or More
Address Bytes
0x00
Address MSB
00
Router ID
The Data Character would look like:
7.0 FPGA ACCESS
The V2 FPGA can be accessed using the V2 JTAG connection using a JTAG/USB Xilinx pod through the V2 PROM JTAG
connector or using the UT699 LEON-3FT on the Aeroflex Gaisler UT699 evaluation board.
Connector J8 is connected to the XC18V04VQ44 Xilinx PROM (44-VTQFP), connector J5 is connected to the JTAG interface
on the Virtex 2 - XC2V500 (FG256/FGG256). The user can determine which access route to the V2 is best suited to their
needs.
Be sure to jumper headers J6, J9, and J10 to ensure proper access from the PROM to the V2 FPGA.
8.0 QUICK START GUIDE