User manual

2
4.0 FUNCTIONAL DIAGRAM
SpW PORTSpW PORTSpW PORTSpW PORT
SpW PORT SpW PORT SpW PORT SpW PORT
UT200SpW4RTR
SpaceWire Router
Clock Network
Manager II
Xilinx V2
Xilinx
PROM
LVDS
UT54LVDS031LV UT54LVDS032LV
Gaisler Board J9 Connector
1.5V Linear
Regulator
Powered from
3.3V
2.5V
Regulator
Powered from
3.3V
2.5V Power Plane 3.3V Power Plane 5.0V Power Plane 1.5V Power Plane
BNC
5.0V
BNC
3.3V
BNC
2.5V
4 LVCMOS Ports
4 TX_CLK_IN
HOST CLK
4 LVDS SpW
HOST PORT
+3.3V +5.0V
+3.3
PIN
GND
JTAG
PAGE 2
PAGE 6
PAGE 1
PAGE 4
PAGE 3
PAGE 5
JTAG
Figure 1. Notional UT200SpW4RTR-EVB block diagram